IS43DR32801B-37CBL-TR

Density 256M
Org 8Mx32
Vcc 1.8V
Type DDR2
Refresh 8K
Speed 37 = 266MHz
Status Prod
Comment
Pkg Pins BGA(126)
Temp. Grade blank = Commercial Grade (0°C to +70°C)
Solder Type L = SnAgCu
Generation B = B
Number Of Words 801 = 8M
CL (CAS Latency) C = 4
Operating Voltage Range DR = 1.8V DDR2
Bus Width 32 = x32
Package Type B = BGA
Product Family 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
Outpack Tape on Reel

IS43DR32801B-37CBL-TR Features

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
  • JEDEC standard 1.8V I/O (SSTL_18-compatible)
  • Double data rate interface: two data transfers per clock cycle
  • Differential data strobe (DQS, DQS)
  • 4-bit prefetch architecture
  • On chip DLL to align DQ and DQS transitions with CK
  • 4 internal banks for concurrent operation
  • Programmable CAS latency (CL) 3, 4, 5, and 6 supported
  • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
  • WRITE latency = READ latency - 1 tCK
  • Programmable burst lengths: 4 or 8
  • Adjustable data-output drive strength, full and reduced strength options
  • On-die termination (ODT) OPTIONS
  • Configuration: 8M x 32 (IS43/46DR32801B - 8K refresh)
  • Package: x32: 126-ball WBGA
  • Timing
    • Cycle time 2.5ns @CL=6, DDR2-800E 3.0ns @CL=5, DDR2-667D 3.75ns @CL=4, DDR2-533C 5.0ns @CL=3, DDR2-400B

Overview

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. The 256Mb DDR2 SDRAM is provided in a wide bus x32 format, designed to offer a smaller footprint and support compact designs.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS43DR32801B-37CBL 47 220 IS43DR32801B-3DBL-TR
IS43DR32801B-37CBLI 58 37 IS43DR32801B-3DBLI 55 5,000
IS43DR32801B-37CBLI-TR IS43DR32801B-3DBLI-TR
IS43DR32801B-3DBL 5,000