IS46DR16128C-3DBA1

Density	2G
Org	128Mx16
Vcc	1.8V
Type	DDR2
Refresh	8K
Speed	3 = 333MHz
Status	Prod
Comment
Pkg Pins	BGA(84)
Temp. Grade	A1 = Automotive Grade (-40°C to +85°C)
Solder Type	blank = Sn/Pb
Number Of Words	128 = 128M
CL (CAS Latency)	D = 5
Operating Voltage Range	DR = 1.8V DDR2
Generation	C = C
Bus Width	16 = x16
Package Type	B = BGA
Product Family	46 = DDR/DDR2/DDR3/DDR4 Automotive grade

Datasheet

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IS46DR16128C-3DBA1 Features

Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, 6, and 7 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5, and 6 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT) OPTIONS
Configuration(s): 256Mx8 (32Mx8x8 banks) IS43/46DR82560C 128Mx16 (16Mx16x8 banks) IS43/46DR16128C
Package: x8: 60-ball BGA (8mm x 10.5mm) x16: 84-ball WBGA (8mm x 12.5mm) Timing
- Cycle time 2.5ns @CL=5 DDR2-800D 3.0ns @CL=5 DDR2-667D

Overview

ISSI's 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

Related Part Number(s)

Description	Description	Available Qty
IS46DR16128C-3DBA1-TR	IS46DR16128C-3DBLA1	6,245
IS46DR16128C-25DBLA1	IS46DR16128C-3DBLA1-TR	7,500
IS46DR16128C-25DBLA1-TR	IS46DR16128C-3DBLA2	1,254
IS46DR16128C-25DBLA2	IS46DR16128C-3DBLA2-TR	7,500
IS46DR16128C-25DBLA2-TR