1. ISSI
  2. DRAM
  3. DDR2 SDRAM
  4. 1.8V Automotive
  5. 256M 32Mx8
  6. BGA(60)
  7. IS46DR83200A

  IS46DR83200A

Datasheet
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Density 256M
Org 32Mx8
Pkg(Pins) BGA(60)
Vcc 1.8V
Refresh 8K
Speed 533, 400
Status Contact
Type DDR2
Number Of Words 3200 = 32M
Operating Voltage Range DR = 1.8V DDR2
Bus Width 8 = x8
Product Family 46 = DDR/DDR2/DDR3/DDR4 Automotive grade
Datasheet
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IS46DR83200A Features

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
  • JEDEC standard 1.8V I/O (SSTL_18-compatible)
  • Double data rate interface: two data transfers per clock cycle
  • Differential data strobe (DQS, DQS)
  • 4-bit prefetch architecture
  • On chip DLL to align DQ and DQS transitions with CK
  • 4 internal banks for concurrent operation
  • Programmable CAS latency (CL) 3, 4, 5, and 6 supported
  • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
  • WRITE latency = READ latency - 1 tCK
  • Programmable burst lengths: 4 or 8
  • Adjustable data-output drive strength, full and reduced strength options
  • On-die termination (ODT) OPTIONS
  • Configuration(s): 32Mx8 (8Mx8x4 banks) IS43/46DR83200A 16Mx16 (4Mx16x4 banks) IS43/46DR16160A
  • Package: x8: 60-ball TW-BGA (8mm x 10.5mm) x16: 84-ball TW-BGA (8mm x 12.5mm) Timing
    • Cycle time 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D 3.75ns @CL=4 DDR2-533C 5.0ns @CL=3 DDR2-400B

Overview

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.