1. ISSI
  2. SRAM
  3. HyperRAM™
  4. 1.7-1.95V
  5. 128M 16Mx8
  6. BGA(24)
  7. IS66WVH16M8DALL-200B1LI

  IS66WVH16M8DALL-200B1LI

Datasheet
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Density 128M
Org 16Mx8
Vcc 1.7-1.95V
Status Prod
Pkg Pins BGA(24)
Speed Mhz 200
Comment Previous Rev IS66/67WVH16M8ALL
Package Code B1 = 24-ball TFBGA
Density Configuration 16M8 = 128Mb /16M x8
ROHS Version L = true
Revision D = D
Product Type WVH = HyperRAM
Temperature Range I = Industrial (-40°C to 85°C)
Speed 200 = 200 MHz
Vdd(V) ALL = 1.8V
Item 66 = Pseudo SRAM/HyperRAM™
Datasheet
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IS66WVH16M8DALL-200B1LI Features

  • 3.0V I/O, 11 bus signals
    • Single ended clock (CK)
  • 1.8V I/O, 12 bus signals
    • Differential clock (CK, CK#)
  • Chip Select (CS#)
  • 8-bit data bus (DQ[7:0])
  • Read-Write Data Strobe (RWDS)
    • Bidirectional Data Strobe / Mask
    • Output at the start of all transactions to indicate refresh latency
    • Output during read transactions as Read Data Strobe
    • Input during write transactions as Write Data Mask
  • RWDS DCARS Timing
    • During read transactions RWDS is offset by a second clock, phase shifted from CK
    • The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye Performance Summary High Performance Up to 400MB/s
  • Double-Data Rate (DDR) - two data transfers per clock
  • 200-MHz clock rate (400 MB/s) at 1.8V VCC 166-MHz clock rate (332 MB/s) at 1.8V VCC
  • 166-MHz clock rate (332 MB/s) at 3.0V VCC
  • Sequential burst transactions
  • Configurable Burst Characteristics ,105°C ,125°C ,105°C/125°C
    • Wrapped burst lengths:
    • 16 bytes (8 clocks)
    • 32 bytes (16 clocks)
    • 64 bytes (32 clocks)
    • 128 bytes (64 clocks)
    • Linear burst
    • Hybrid option - one wrapped burst followed by linear burst
    • Wrapped or linear burst type selected in each transaction
    • Configurable output drive strength
  • Temperature Grade
    • Industrial: -40°C to +85°C Auto (A2) Grade: -40°C to +105°C Auto (A3) Grade: -40°C to +125°C

Overview

The IS66/67WVH16M8DALL/BLL are integrated memory device containing 128Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 16M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and Automotive applications.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS66WVH16M8DALL-200B1LI-TR IS66WVH16M8DALL-166B1LI-TR
IS66WVH16M8DALL-133B2LI IS66WVH16M8DBLL
IS66WVH16M8DALL-133B2LI-TR IS66WVH16M8DBLL-TR
IS66WVH16M8DALL-166B1LI