IS43LD16256A-18BPL-TR

Density 4G
Org 256Mx16
Vcc 1.2/1.8V
Type LPDDR2
Refresh 8K
Status S=NOW
Pkg Pins PoP(168)
Speed Mhz 533, 400, 333
Comment Previous Rev
Bus Width 16 = x16
Product Family 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
Temp. Grade blank = Commercial Grade (0°C to +70°C)
Solder Type L = SnAgCu
Number Of Words 256 = 256M
Speed 18 = 533MHz
Operating Voltage Range LD = 1.2V - 1.8V LPDDR2
Generation A = A
Package Type BP = PoP BGA
Outpack Tape on Reel

IS43LD16256A-18BPL-TR Features

  • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V
  • High Speed Un-terminated Logic(HSUL_12) I/O Interface
  • Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O)
  • Four-bit Pre-fetch DDR Architecture
  • Multiplexed, double data rate, command/ad- dress inputs
  • Eight internal banks for concurrent operation
  • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
  • Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16)
  • ZQ Calibration
  • On-chip temperature sensor to control self re- fresh rate
  • Partial
    • array self refresh(PASR)
  • Deep power-down mode(DPD)
  • Operation Temperature Commercial (TC = 0°C to 85°C) Industrial (TC = -40°C to 85°C) Automotive, A1 (TC = -40°C to 85°C) Automotive, A2 (TC = -40°C to 105°C) options

Overview

Clock: CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK. Single Data Rate (SDR) inputs, CS# and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK and CK#. The positive Clock edge is defined by the crosspoint of a rising CK and a falling CK#. The negative Clock edge is defined by the crosspoint of a falling CK and a rising CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. See Command Truth Table for command code descriptions. CKE is sampled at the positive Clock edge. Chip Select: CS# is considered part of the command code. See Command Truth Table for command code descriptions. CS# is sampled at the positive Clock edge. DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. See Command Truth Table for command code descriptions. Data Inputs/Output: Bi-directional data bus.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS43LD16256A-18BPL IS46LD16256A-18BPLA1-TR
IS43LD16256A-18BPLI256M IS46LD16256A-18BPLA2
IS43LD16256A-18BPLI256M-TR IS46LD16256A-18BPLA2-TR
IS43LD16256A-25BPL IS46LD16256A-25BPLA1
IS43LD16256A-25BPL-TR IS46LD16256A-25BPLA1-TR
IS43LD16256A-25BPLI256M IS46LD16256A-25BPLA2
IS43LD16256A-25BPLI256M-TR IS46LD16256A-25BPLA2-TR
IS46LD16256A-18BPLA1