1. ISSI
  2. Mobile DRAM
  3. LPDDR2 SDRAM
  4. PowerSaver™
  5. 1.2/1.8V
  6. 4G 128Mx32
  7. BGA(134), PoP(168)
  8. IS43LD32128B-TR

  IS43LD32128B-TR

Datasheet
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Density 4G
Org 128Mx32
Vcc 1.2/1.8V
Type LPDDR2
Refresh 8K
Status S=NOW
Pkg Pins BGA(134), PoP(168)
Speed Mhz 533, 400
Comment Previous Rev
Number Of Words 128 = 128M
Operating Voltage Range LD = 1.2V - 1.8V LPDDR2
Generation TR = TR
Bus Width 32 = x32
Product Family 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
Outpack Tape on Reel
Datasheet
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IS43LD32128B-TR Features

  • Hardware Features
  • - SCLK Input: Serial clock input - SIO0
    • SIO3: Serial Data Input or Serial Data Output - DQSM: - Output during command, address transactions as Refresh Collision Indicator - Output during read data transactions as Read Data Strobe - Input during write data transactions as Write Data Mask - RESET#: Hardware Reset pin
  • Temperature Grades
  • - - Auto (A2) Grade: -40°C to +105°C Industrial: -40°C to +85°C
  • Industry Standard PACKAGE
  • - B = 24-ball TFBGA 6x8mm 5x5 Array - M = 16-pin 300mil SOIC(1) - KGD (Call Factory) Note: 1. 133MHz (max.) for 16-pin SOIC package
  • Industry Standard Serial Interface
  • - Quad DDR (x4 xSPI) Interface: Command (1 byte) =SDR Address (2-byte) & Data = DDR - Low Signal Counts :7 Signal pins (CS#, SCLK, DQSM, SIO0~SIO3)
  • High Performance
  • - On chip ECC (chunk size = 4 bit): 1-bit correction and 2-bit detection - Double Data Rate (DDR) Operation: 200MHz (200MB/s) at 1.8V VCC (1) 133MHz (133MB/s) at 3.0V VCC - Source Synchronous Output signal during Read Operation (DQSM) - Data Mask during Write Operation (DQSM) - Configurable Latency for Read/Write Operation - Supports Variable Latency mode and Fixed Latency mode - Configurable Drive Strength - Supports Wrapped Burst mode and Continuous mode - Supports Deep Power Down mode - Hidden Refresh
  • Burst Operation
  • - Configurable Wrapped Burst Length : 16, 32, 64, and 128 - Continuous Operation: - Continues Read operation until the end of array address (No Wrapped) - Continues Write operation even after the end of array address (Wrapped to first address)

Overview

The IS66/67WVQ4M4EDALL/BLL are integrated memory device containing 16Mb Pseudo Static Random Access Memory, using a self-refresh DRAM array organized as 2M words by 8 bits. The device supports Quad DDR interface, which is compatible with JEDEC standard x4 xSPI Flash. The device supports Very Low Signal Count (7 signal pins; SCLK, CS#, DQSM, and 4 SIOs) + optional ERR, Hidden Refresh Operation, and Automotive temperature (A2, -40°C to +105°C) operation. Due to DDR operation, minimum transferred data size is a byte (8 bits) through 4 SIO pins. PERFORMANCE SUMMARY.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS43LD32128B IS43LD32128B-25BL
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IS43LD32128B-18BL-TR IS43LD32128B-25BLI
IS43LD32128B-18BLI IS43LD32128B-25BLI-TR
IS43LD32128B-18BLI-TR IS43LD32128B-25BPL
IS43LD32128B-18BPL IS43LD32128B-25BPL-TR
IS43LD32128B-18BPL-TR IS43LD32128B-25BPLI128M
IS43LD32128B-18BPLI128M IS43LD32128B-25BPLI128M-TR
IS43LD32128B-18BPLI128M-TR