IS43LD32640B-25BPL

Density 2G
Org 64Mx32
Vcc 1.2/1.8V
Type LPDDR2
Refresh 8K
Status Prod
Pkg Pins BGA(134), PoP(168)
Speed Mhz 533, 400, 333
Comment Previous Rev
Temp. Grade blank = Commercial Grade (0°C to +70°C)
Solder Type L = SnAgCu
Generation B = B
Number Of Words 640 = 64M
Speed 25 = 400MHz
Operating Voltage Range LD = 1.2V - 1.8V LPDDR2
Bus Width 32 = x32
Package Type BP = PoP BGA
Product Family 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade

IS43LD32640B-25BPL Features

  • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V
  • High Speed Un-terminated Logic(HSUL_12) I/O Interface
  • Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O)
  • Four-bit Pre-fetch DDR Architecture
  • Multiplexed, double data rate, command/ad- dress inputs
  • Eight internal banks for concurrent operation
  • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
  • Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16)
  • ZQ Calibration
  • On-chip temperature sensor to control self re- fresh rate
  • Partial
    • array self refresh(PASR)
  • Deep power-down mode(DPD)
  • Operation Temperature Commercial (TC = 0°C to 85°C) Industrial (TC = -40°C to 85°C) Automotive, A1 (TC = -40°C to 85°C) Automotive, A2 (TC = -40°C to 105°C) Automotive, A25 (TC = -40°C to 115°C)(3) options

Overview

Clock: CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK. Single Data Rate (SDR) inputs, CS# and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK and CK#. The positive Clock edge is defined by the crosspoint of a rising CK and a falling CK#. The negative Clock edge is defined by the crosspoint of a falling CK and a rising CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. See Command Truth Table for command code descriptions. CKE is sampled at the positive Clock edge. Chip Select: CS# is considered part of the command code. See Command Truth Table for command code descriptions. CS# is sampled at the positive Clock edge. DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. See Command Truth Table for command code descriptions. Data Inputs/Output: Bi-directional data bus.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS43LD32640B-25BPL-TR IS46LD32640B-18BLA25-TR
IS43LD32640B-18BL 1,026 IS46LD32640B-18BPLA1
IS43LD32640B-18BL-TR IS46LD32640B-18BPLA1-TR
IS43LD32640B-18BLI 1,026 IS46LD32640B-18BPLA2
IS43LD32640B-18BLI-TR IS46LD32640B-18BPLA2-TR
IS43LD32640B-18BPL IS46LD32640B-18BPLA25
IS43LD32640B-18BPL-TR IS46LD32640B-18BPLA25-TR
IS43LD32640B-18BPLI 3 IS46LD32640B-25BLA1
IS43LD32640B-18BPLI-TR IS46LD32640B-25BLA1-TR
IS43LD32640B-25BL IS46LD32640B-25BLA2
IS43LD32640B-25BL-TR IS46LD32640B-25BLA2-TR
IS43LD32640B-25BLI IS46LD32640B-25BLA25
IS43LD32640B-25BLI-TR IS46LD32640B-25BLA25-TR
IS43LD32640B-25BPLI 159 IS46LD32640B-25BPLA1
IS43LD32640B-25BPLI-TR IS46LD32640B-25BPLA1-TR
IS46LD32640B-18BLA1 IS46LD32640B-25BPLA2
IS46LD32640B-18BLA1-TR IS46LD32640B-25BPLA2-TR
IS46LD32640B-18BLA2 IS46LD32640B-25BPLA25
IS46LD32640B-18BLA2-TR IS46LD32640B-25BPLA25-TR
IS46LD32640B-18BLA25