IS66WVO8M8EDBLL-133BLI

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Density 64M
Org 8Mx8
Vcc 2.7-3.6V
Status Prod
Pkg Pins BGA(24)
Speed Mhz 166
Comment Previous Rev ECC Based
Item 66 = Pseudo SRAM/HyperRAM™
Revision D = D
ROHS Version L = true
Product Type WVO = OctalRAM
Temperature Range I = Industrial (-40°C to 85°C)
Speed 133 = 133 MHz
Vdd(V) BLL = 3V
Density Configuration 8M8 = 64Mb /8M x8
Package Code B = 24-ball TFBGA 6x8mm 5x5 ball array

IS66WVO8M8EDBLL-133BLI Features

  • Industry Standard Serial Interface
  • - Octal Peripheral Interface (OPI) Protocol - Low Signal Counts :11 Signal pins (CS#, SCLK, DQSM, SIO0~SIO7)+ optional ERR output
  • High Performance
  • - On chip ECC (chunk size = 4 bit): 1-bit correction and 2-bit detection - Double Transfer Rate (DTR) Operation - Up to 166MHz (332MB/s) - Source Synchronous Output signal during Read Operation (DQSM) - Configurable Latency for Read/Write Operation)
  • Hardware Features
  • - SCLK Input: Serial clock input - SIO0 - SIO7: Serial Data Input or Serial Data Output - DQSM: - Output during command, address transactions as Refresh Collision Indicator - Output during read data transactions as Read Data Strobe - Input during write data transactions as Write Data Mask - RESET#: Hardware Reset pin - ERR: ECC Event indicator - Supports Variable Latency mode and
  • Temperature Grades
  • - - Auto (A2) Grade: -40°C to +105°C Industrial: -40°C to +85°C
  • Industry Standard PACKAGE
  • - B = 24-ball TFBGA 6x8mm 5x5 Array - KGD (Call Factory) Fixed Latency mode - Configurable Drive Strength - Supports Wrapped Burst mode and Continuous Burst mode - Supports Deep Power Down mode - Hidden Refresh
  • Burst Operation
  • - Configurable Wrapped Burst Length : 16, 32, 64, and 128 - Word Order Burst Sequence - Continuous Burst Operation: - Continues Read operation until the end of array address - Continues Write operation even after the end of array address

Overview

The IS66/67WVO8M8EDALL/BLL are integrated memory device containing 64Mb Pseudo Static Random Access Memory with On-chip ECC, using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports Octal Peripheral Interface (Address, Command, and Data through 8 SIO pins), Very Low Signal Count (11 signal pins; SCLK, CS#, DQSM, and 8 SIOs)+ optional ERR signal, Hidden Refresh Operation, and Automotive temperature (A2, -40°C to +105°C) operation. Due to DTR operation, minimum transferred data size is word (16 bits) base instead of byte (8 bits) base. PERFORMANCE SUMMARY.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS66WVO8M8EDBLL-133BLI-TR IS66WVO8M8EDBLL-166BLI-TR
IS66WVO8M8EDBLL-166BLI