1. ISSI
  2. SRAM
  3. Octal RAM
  4. OctalRAM
  5. 2.7-3.6V
  6. 64M 8Mx8
  7. BGA(24)
  8. IS67WVO8M8DBLL-133BLA3-TR

  IS67WVO8M8DBLL-133BLA3-TR

Datasheet
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Density 64M
Org 8Mx8
Vcc 2.7-3.6V
Status Prod
Pkg Pins BGA(24)
Speed Mhz 166
Comment Previous Rev
Package Code B = 24-ball TFBGA 6x8mm 5x5 ball array
Density Configuration 8M8 = 64Mb /8M x8
ROHS Version L = true
Revision D = D
Product Type WVO = OctalRAM
Temperature Range A3 = Automotive (-40°C to +125°C)
Speed 133 = 133 MHz
Vdd(V) BLL = 3V
Item 67 = Automotive PSRAM/HyperRAM™
Outpack Tape on Reel
Datasheet
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IS67WVO8M8DBLL-133BLA3-TR Features

  • Industry Standard Serial Interface
  • - Octal Peripheral Interface (OPI) Protocol - Low Signal Counts :11 Signal pins (CS#,
  • Hardware Features
  • - SCLK Input: Serial clock input - SIO0 - SIO7: SCLK, DQSM, SIO0~SIO7)
  • High Performance
  • - Up to 400MB/s - Double Transfer Rate (DTR) Operation - 200MHz (400MB/s) at 1.8V VCC - 166MHz (332MB/s) at 3.0V VCC - Source Synchronous Output signal during Read Operation (DQSM) Serial Data Input or Serial Data Output - DQSM: - Output during command, address transactions as Refresh Collision Indicator - Output during read data transactions as Read Data Strobe - Input during write data transactions as Write Data Mask - Data Mask during Write Operation - RESET#: Hardware Reset pin Industrial: -40°C to +85°C
  • Temperature Grades
  • - - Auto (A2) Grade: -40°C to +105°C - Auto (A3) Grade: -40°C to +125°C
  • Industry Standard PACKAGE
  • - B = 24-ball TFBGA 6x8mm 5x5 Array - KGD (Call Factory) (DQSM) - Configurable Latency for Read/Write Operation) - Supports Variable Latency mode and Fixed Latency mode - Configurable Drive Strength - Supports Wrapped Burst mode and Continuous Burst mode - Supports Deep Power Down mode - Hidden Refresh
  • Burst Operation
  • - Configurable Wrapped Burst Length : 16, 32, 64, and 128 - Word Order Burst Sequence - Continuous Burst Operation: - Continues Read operation until the end of array address - Continues Write operation even after the end of array address

Overview

The IS66/67WVO8M8DALL/BLL are integrated memory device containing 64Mb Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports Octal Peripheral Interface (Address, Command, and Data through 8 SIO pins), Very Low Signal Count (11 signal pins; SCLK, CS#, DQSM, and 8 SIOs), Hidden Refresh Operation, and Automotive temperature (A3, -40°C to +125°C) operation. Due to DTR operation, minimum transferred data size is word (16 bits) base instead of byte (8 bits) base. PERFORMANCE SUMMARY.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS67WVO8M8DBLL-133BLA3 IS67WVO8M8DBLL-166BLA2-TR
IS67WVO8M8DBLL-133BLA2 IS67WVO8M8DBLL-166BLA3
IS67WVO8M8DBLL-133BLA2-TR IS67WVO8M8DBLL-166BLA3-TR
IS67WVO8M8DBLL-166BLA2