IS42S16160L-7BLI-TR
Features
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Clock frequency: 200, 166, 143, 133 MHz ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
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Fully synchronous; all signals referenced to a outputs signals refer to the rising edge of the clock input.
positive clock edge The 256Mb SDRAM is organized as follows.
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Internal bank for hiding row access/precharge
IS42S83200L IS42S16160L
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Single Power supply: 3.3V + 0.3V
8M x 8 x 4 Banks 4M x16x4 Banks
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LVTTL interface
54-pin TSOPII 54-pin TSOPII
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Programmable burst length
54-ball BGA 54-ball BGA
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Programmable burst sequence:
KEY TIMING PARAMETERS
Sequential/Interleave
Parameter -5 -6 -7 Unit
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Auto Refresh (CBR)
Clk Cycle Time
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Self Refresh CAS Latency = 3 5 6 7 ns
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8K refresh cycles every 32 ms (A2 grade) or CAS Latency = 2 10 10 7.5 ns
64 ms (commercial, industrial, A1 grade) Clk Frequency
CAS Latency = 3 200 166 143 Mhz
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Random column address every clock cycle
CAS Latency = 2 100 100 133 Mhz
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Programmable CAS latency (2, 3 clocks) Access Time from Clock
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Burst read/write and burst read/single write CAS Latency = 3 5 5.4 5.4 ns
operations capability CAS Latency = 2 5 5.4 5.4 ns
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Burst termination by burst stop and precharge
command
ADDRESS TABLE
OPTIONS Parameter 32M x 8 16M x 16
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Package: Configuration 8M x 8 x 4 4M x 16 x 4
54-pin TSOP-II banks banks
54-ball BGA Refresh Count
Com./Ind. 8K/64ms 8K/64ms