IS42S32800L-7BLI
Features
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Clock frequency: 200, 166, 143, 133 MHz ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
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Fully synchronous; all signals referenced to a outputs signals refer to the rising edge of the clock input.
positive clock edge The 256Mb SDRAM is organized in 2Meg x 32 bit x 4
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Internal bank for hiding row access/precharge Banks.
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Single Power supply: 3.3V + 0.3V
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LVTTL interface KEY TIMING PARAMETERS
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Programmable burst length Parameter -5 -6 -7 Unit
- (1, 2, 4, 8, full page) Clk Cycle Time
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Programmable burst sequence: CAS Latency = 3 5 6 7 ns
CAS Latency = 2 10 10 7.5 ns
Sequential/Interleave
Clk Frequency
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Auto Refresh (CBR) CAS Latency = 3 200 166 143 Mhz
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Self Refresh CAS Latency = 2 100 100 133 Mhz
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4096 refresh cycles every 16ms (A2 grade) or Access Time from Clock
64 ms (Commercial, Industrial, A1 grade) CAS Latency = 3 4.8 5.4 5.4 ns
CAS Latency = 2 6.5 6.5 5.5 ns
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Random column address every clock cycle
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Programmable CAS latency (2, 3 clocks)
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Burst read/write and burst read/single write
operations capability ADDRESS TABLE
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Burst termination by burst stop and precharge Parameter 8M x 32
command Configuration 2M x 32 x 4 banks
OPTIONS Refresh Count Com./Ind. 4K / 64ms
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Package: A1 4K / 64ms
90-ball TF-BGA A2 4K / 16ms
86-pin TSOP2 Row Addresses A0