IS42S83200L-5BL

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Density	256M
Org	32Mx8
Vcc	3.3V
Type	SDR
Refresh	8K
Speed	5 = 200MHz
Status	S=Q2/24
Comment
Pkg Pins	TSOP2(54), BGA(54)
Temp. Grade	blank = Commercial Grade (0°C to +70°C)
Solder Type	L = SnAgCu
Number Of Words	3200 = 32M
Operating Voltage Range	S = 3.3V SDR
Generation	L = L
Bus Width	8 = x8
Package Type	B = BGA
Product Family	42 = SDR Commercial/Industrial grade

IS42S83200L-5BL Features

Clock frequency: 200, 166, 143, 133 MHz ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and
Fully synchronous; all signals referenced to a outputs signals refer to the rising edge of the clock input. positive clock edge The 256Mb SDRAM is organized as follows.
Internal bank for hiding row access/precharge IS42S83200L IS42S16160L
Single Power supply: 3.3V + 0.3V 8M x 8 x 4 Banks 4M x16x4 Banks
LVTTL interface 54-pin TSOPII 54-pin TSOPII
Programmable burst length 54-ball BGA 54-ball BGA
- (1, 2, 4, 8, full page)
Programmable burst sequence: KEY TIMING PARAMETERS Sequential/Interleave Parameter -5 -6 -7 Unit
Auto Refresh (CBR) Clk Cycle Time
Self Refresh CAS Latency = 3 5 6 7 ns
8K refresh cycles every 32 ms (A2 grade) or CAS Latency = 2 10 10 7.5 ns 64 ms (commercial, industrial, A1 grade) Clk Frequency CAS Latency = 3 200 166 143 Mhz
Random column address every clock cycle CAS Latency = 2 100 100 133 Mhz
Programmable CAS latency (2, 3 clocks) Access Time from Clock
Burst read/write and burst read/single write CAS Latency = 3 5 5.4 5.4 ns operations capability CAS Latency = 2 5 5.4 5.4 ns
Burst termination by burst stop and precharge command ADDRESS TABLE OPTIONS Parameter 32M x 8 16M x 16
Package: Configuration 8M x 8 x 4 4M x 16 x 4 54-pin TSOP-II banks banks 54-ball BGA Refresh Count Com./Ind. 8K/64ms 8K/64ms