IS45S16400N-5BLA1
Features
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Clock frequency: 200, 166, 143, 133 MHz ISSI's 64Mb Synchronous DRAM is organized as 1,048,576
bits x 16-bit x 4-bank for improved performance. The
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Fully synchronous; all signals referenced to a
synchronous DRAMs achieve high-speed data transfer
positive clock edge using pipeline architecture. All inputs and outputs signals
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Internal bank for hiding row access/precharge refer to the rising edge of the clock input.
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Single 3.3V power supply
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LVTTL interface
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Programmable burst length
- (1, 2, 4, 8, full page) KEY TIMING PARAMETERS
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Programmable burst sequence: Parameter -5 -6 -7 Unit
Sequential/Interleave Clk Cycle Time
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Self refresh modes CAS Latency = 3 5 6 7 ns
CAS Latency = 2 7.5 7.5 7.5 ns
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Auto refresh (CBR)
Clk Frequency
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4096 refresh cycles every 64 ms (Com, Ind, A1
CAS Latency = 3 200 166 143 Mhz
grade) or 16ms (A2 grade) CAS Latency = 2 133 133 133 Mhz
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Random column address every clock cycle Access Time from Clock
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Programmable CAS latency (2, 3 clocks) CAS Latency = 3 4.8 5.4 5.4 ns
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Burst read/write and burst read/single write CAS Latency = 2 5.4 5.4 5.4 ns
operations capability
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Burst termination by burst stop and precharge
command
ADDRESS TABLE
OPTIONS
Parameter 4M x 16
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Green Package:
Configuration 1M x 16 x 4
54-pin TSOP II banks
54-ball TF-BGA (8mm x 8mm) Refresh Count
60-ball TF-BGA (10.1mm x 6.4mm) Com./Ind. 4K/64ms