IS45S32200N-7TLA1-TR
Features
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Clock frequency: 200, 166, 143, 133 MHz ISSI's 64Mb Synchronous DRAM IS42/45S32200N is
organized as 524,288 bits x 32-bit x 4-bank for improved
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Fully synchronous; all signals referenced to a performance.The synchronous DRAMs achieve high-speed
positive clock edge data transfer using pipeline architecture. All inputs and
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Internal bank for hiding row access/precharge outputs signals refer to the rising edge of the clock input.
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Single 3.3V power supply
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LVTTL interface KEY TIMING PARAMETERS
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Programmable burst length: Parameter -5 -6 -7 Unit
(1, 2, 4, 8, full page) Clk Cycle Time
CAS Latency = 3 5 6 7 ns
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Programmable burst sequence:
Sequential/Interleave CAS Latency = 2 7.5 7.5 7.5 ns
Clk Frequency
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Self refresh modes CAS Latency = 3 200 166 143 Mhz
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4096 refresh cycles every 16ms (A2 grade) or CAS Latency = 2 133 133 133 Mhz
64ms (Commercia, Industrial, A1 grade) Access Time from Clock
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Random column address every clock cycle CAS Latency = 3 4.8 5.4 5.4 ns
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Programmable CAS latency (2, 3 clocks) CAS Latency = 2 5.4 5.4 5.4 ns
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Burst read/write and burst read/single write
operations capability ADDRESS TABLE
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Burst termination by burst stop and precharge Parameter 2M x 32
command Configuration 512K x 32 x 4 banks
Refresh Count Com./Ind. 4K / 64ms
OPTIONS A1 4K / 64ms
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Green Packages: A2 4K / 16ms
86-pin TSOP-II Row Addresses A0
- A10
90-ball TF-BGA Column Addresses A0
- A7