IS45S32400J-7TLA2-TR

Org	4Mx32
Pkg(Pins)	TSOP
Vcc	3.3V
Refresh	4K
Speed	7 = 143MHz
No. of Words	4M
Solder	100% matte Sn
Status	S=Q3/17
Outpack	Tape on Reel
Type	SDR
Bus Width	32 = x32
Temp.Range	Automotive Grade (-40C to +105°C)
Generation/Rev	J
Product Family	45 = SDR Automotive grade
Temp. Grade	A2 = Automotive Grade (-40°C to +105°C)
Solder Type	L = 100% matte Sn
Number Of Words	400 = 4M
Operating Voltage Range	S = 3.3V SDR
Generation	J = J
Package Type	T = TSOP

Datasheet

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IS45S32400J-7TLA2-TR Features

Clock frequency: 166, 143, 133 MHz
Fully synchronous; all signals referenced to a positive clock edge
Internal bank for hiding row access/precharge
Single Power supply: 3.3V + 0.3V
LVTTL interface
Programmable burst length
- (1, 2, 4, 8, full page)
Programmable burst sequence: Sequential/Interleave
Auto Refresh (CBR)
Self Refresh
4096 refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade)
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write operations capability
Burst termination by burst stop and precharge command OPTIONS
Package: 86-pin TSOP-II 90-ball TF-BGA

Overview

ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks.