IS46LQ16256BL

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Density	4G
Org	Single Channel (1x16)
Vcc	0.6V/1.1V/1.8V
Type	LPDDR4X
Speed	4266, 3733, 3200
Status	S=Q2/22
Pkg Pins	BGA(200)
Number Of Words	256 = 256M
Operating Voltage Range	LQ = 1.1V LPDDR4
Bus Width	16 = x16
Product Family	46 = DDR/DDR2/DDR3/DDR4 Automotive grade

Datasheet

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IS46LQ16256BL Features

Configuration: - 256
- 8 internal banks per each channel Mb x16 x 2 channels
On-Chip ECC:
- Single-bit error correction (per 64-bits)
Low-voltage Core and I/O Power Supplies VDD1 = 1.70-1.95V VDD2 = 1.06-1.17V VDDQ = 1.06-1.17V (LPDDR4) VDDQ = 0.57-0.65V (LPDDR4X) LVSTL(Low Voltage Swing Terminated Logic) I/O Interface Internal VREF and VREF Training
Dynamic ODT : DQ ODT :VSSQ Termination CA ODT :VSS Termination
Max. Clock Frequency : 1.6GHz (3.2Gbps)
16n Pre-fetch DDR architecture
Single data rate (multiple cycles) command/ address bus
Bidirectional/differential data strobe per byte of data (DQS/DQS#)
Programmable burst lengths (16 or 32)
ZQ Calibration
Operation Temperature Industrial (TC = -40°C to 95°C) Automotive, A1 (TC = -40°C to 95°C) Automotive, A2 (TC = -40°C to 105°C) Automotive, A3 (TC = -40°C to 125°C)
On-chip temperature sensor whose status can be read from MR4

Overview

The IS43/46LQ32256EA and IS43/46LQ32256EAL are 8Gbit CMOS LPDDR4 SDRAM. The device is orga- nized as 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-da- ta-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.

IS46LQ16256BL Features

Overview

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