Overview
The IS43LD16256A/32128A is 4Gbit CMOS LPDDR2
DRAM. The device is organized as 8 banks of 32Meg
words of 16bits or 16Meg words of 32bits. This product
uses a double-data-rate architecture to achieve high-
speed operation. The double data rate architecture is
essentially a 4N prefetch architecture with an interface
designed to transfer two data words per clock cycle
at the I/O pins. This product offers fully synchronous
operations referenced to both rising and falling edges of
the clock. The data paths are internally pipelined and 4n
bits prefetched to achieve very high bandwidth.