1. ISSI
  2. SRAM
  3. Synchronous SRAM
  4. No-Wait(ZBT)
  5. 2.5V
  6. QFP(100), BGA(165, 209)
  7. IS61NVF51236-7-TR

  IS61NVF51236-7-TR

Datasheet
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Org 512Kx36
Pkg(Pins) QFP(100), BGA(165, 209)
tKQ 6.5, 7.5
Vcc 2.5V
VccQ 2.5V
Models IBIS, BSDL
Status Prod
Comment F
Outpack Tape on reel
Speed(Mhz) 133, 117
Datasheet
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IS61NVF51236-7-TR Features

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single Read/Write control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages
  • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single Read/Write control pin , Clock controlled, registered address,