IS46LR16320C-6BLA2-TR

容量 512M
規格 32Mx16
電壓 1.8V
類型 MDDR
刷新 8K
狀態 Prod
腳位數 BGA(60)
速度Mhz 200, 166, 133
評論上一篇 IS43/46LR16320B
温度等级 A2 = Automotive Grade (-40°C to +105°C)
焊料類型 L = SnAgCu
Generation C = C
字數 320 = 32M
速度 6 = 166MHz
工作電壓範圍 LR = 1.8V mobile DDR (LPDDR)
總線寬度 16 = x16
腳位/封裝 B = BGA
產品系列 46 = DDR/DDR2/DDR3/DDR4 Automotive grade
外包裝 Tape on Reel

IS46LR16320C-6BLA2-TR 特徵

  • JEDEC standard 1.8V power supply
  • VDD = 1.8V, VDDQ = 1.8V
  • Four internal banks for concurrent operation
  • MRS cycle with address key programs
  • - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave)
  • Fully differential clock inputs (CK, /CK)
  • All inputs except data & DM are sampled at the rising edge of the system clock
  • Data I/O transaction on both edges of data strobe
  • Bidirectional data strobe per byte of data (DQS)
  • DM for write masking only
  • Edge aligned data & data strobe output
  • Center aligned data & data strobe input
  • 64ms refresh period (8K cycle)
  • Auto & self refresh
  • Concurrent Auto Precharge
  • Maximum clock frequency up to 200MHZ
  • Maximum data rate up to 400Mbps/pin
  • Power Saving support
  • Status Register Read (SRR)
  • LVCMOS compatible inputs/outputs

概觀

The IS43/46LR16320C is 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 8,388,608 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

 

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