IS61WV25616LEBLL-15BI-TR

容量 4M
電壓 2.4~3.6V
狀態 Prod
I / O寬度 x16
腳位數 TSOP2(44), BGA(48)
溫度範圍 -40 to 125°C
速度Mhz Ns 12, 15ns
評論上一篇 Latched SRAM

IS61WV25616LEBLL-15BI-TR 特徵

  • High-speed access time: 12ns, 15ns
  • Single power supply
    • 2.4V-3.6V VDD
  • Ultra Low Standby Current with ZZ# pin
  • - IZZ = 30uA (typ.)
  • Error Detection and Correction with optional ERR1/ERR2 output pin:
  • - ERR1 pin indicates 1-bit error detection and correction. - ERR2 pin indicates multi-bit error detection
  • ALE# pin to latch Address & CS# signals. Industrial and Automotive temperature support

概觀

Latched SRAM is the SRAM, which can latch Address/CS# inputs via ALE# pin. The address/CS# inputs will be latched when ALE# is Low, so the host could access another bus (Address/CS#) for the remaining operation period. ADDRESS LATCH ENABLE (ALE#) FUNCTION When Address Latch Enable signal (ALE#) is High, latch is transparent, and external address and CS# signals go through Address and CS# path to access memory cell array, and the device acts like normal Asynchronous SRAM. When Address Latch Enable signal (ALE#) is Low, external address and CS# signals are latched, and those external signals are getting isolated from internal device (all other signals are not latched). Memory controller does not have to maintain external address and CS# signals after ALE# goes Low during entire operation cycle, which could improve effective operation cycle time. Also it could reduce potential glitch problem to achieve stable operation. WRITE MODE Write operation issues with Chip Select (CS#) Low and Write Enable (WE#) Low. The input and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is Low. UB# and LB# enables a byte write feature. By enabling LB# Low, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being Low, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip Select (CS#) Low and Write Enable (WE#) High. When OE# is Low, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# Low, data from memory appears on I/O0-7. And with UB# being Low, data from memory appears on I/O8-15. OE# is Asynchronous pin to control output time. In the READ mode, output buffers can be turned off by pulling OE# High. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. STANDBY MODE Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1, or ISB2. SNOOZE MODE Device enters Snooze mode from Standby mode when asserting ZZ# Low, tZZI (100ns Min) after CS# High. Upon assertion of ZZ# Low, the device enters Snooze mode from Standby mode after tZZ (1ms Min.). During Snooze mode, the device must remain standby mode (CS# High), and ZZ# must remain asserted Low. Snooze mode can minimize Standby power consumption. To exit Snooze mode, ZZ# must be de-asserted (High). The device returns to Standby mode from Snooze mode and CS# can be asserted Low, tZZO (1ms Min.) after de-assertion of ZZ# High. SNOOZE MODE WAVEFORM.

 

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