IS65WV25616EHBLL-55B3A3

Density 4M
Org 256Kx16
Vcc 1.65-3.6V
Status S=NOW
Pkg Pins TSOP2(44), BGA(48)
Speed Ns 45, 55
Comment Previous Rev ECC based SRAM

IS65WV25616EHBLL-55B3A3 Features

  • High-speed access time: 45ns, 55ns
  • CMOS low power operation
    • Operating Current: 25 mA (max.)
    • CMOS Standby Current: 3.2 uA (typ., 25°C)
  • TTL compatible interface levels
  • Single power supply
    • 1.65V-2.2V VDD (IS62/65WV25616EHALL)
    • 2.2V-3.6V VDD (IS62/65WV25616EHBLL)
  • Optional ERR1/ERR2 pin:
    • ERR1: indicates 1-bit error detection and correction
    • ERR2: indicates 2-bit error detection
  • Three state outputs
  • Commercial, Industrial and Automotive temperature support

Overview

SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth All function description including Table is based on 2 Chip Select option. STANDBY MODE Device enters standby mode when deselected (CS1# HIGH or CS2 LOW or both UB# and LB# are HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1 or ISB2. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. ERROR DETECTION AND ERROR CORRECTION.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS62WV25616EHALL-55B2I IS62WV25616EHALL-55T2LI
IS62WV25616EHALL-55B2I-TR IS62WV25616EHALL-55T2LI-TR
IS62WV25616EHALL-55B2L IS62WV25616EHALL-55TL
IS62WV25616EHALL-55B2L-TR IS62WV25616EHALL-55TL-TR
IS62WV25616EHALL-55B2LI IS62WV25616EHALL-55TLI
IS62WV25616EHALL-55B2LI-TR IS62WV25616EHALL-55TLI-TR
IS62WV25616EHALL-55B3I IS62WV25616EHBLL-45B2I
IS62WV25616EHALL-55B3I-TR IS62WV25616EHBLL-45B2I-TR
IS62WV25616EHALL-55B3L IS62WV25616EHBLL-45B2L
IS62WV25616EHALL-55B3L-TR IS62WV25616EHBLL-45B2L-TR
IS62WV25616EHALL-55B3LI IS62WV25616EHBLL-45B2LI
IS62WV25616EHALL-55B3LI-TR IS62WV25616EHBLL-45B2LI-TR
IS62WV25616EHALL-55B4I IS62WV25616EHBLL-45B3I
IS62WV25616EHALL-55B4I-TR IS62WV25616EHBLL-45B3I-TR
IS62WV25616EHALL-55B4L IS62WV25616EHBLL-45B3L
IS62WV25616EHALL-55B4L-TR IS62WV25616EHBLL-45B3L-TR
IS62WV25616EHALL-55B4LI IS62WV25616EHBLL-45B3LI
IS62WV25616EHALL-55B4LI-TR IS62WV25616EHBLL-45B3LI-TR
IS62WV25616EHALL-55BI IS62WV25616EHBLL-45B4I
IS62WV25616EHALL-55BI-TR IS62WV25616EHBLL-45B4I-TR
IS62WV25616EHALL-55BL IS62WV25616EHBLL-45B4L
IS62WV25616EHALL-55BL-TR IS62WV25616EHBLL-45B4L-TR
IS62WV25616EHALL-55BLI IS62WV25616EHBLL-45B4LI
IS62WV25616EHALL-55BLI-TR IS62WV25616EHBLL-45B4LI-TR
IS62WV25616EHALL-55T2L IS62WV25616EHBLL-45BI
IS62WV25616EHALL-55T2L-TR
Show All (76)