IS46DR16160B-3DBLA2-TR

Density 256M
Org 16Mx16
Vcc 1.8V
Type DDR2
Refresh 8K
Speed 3 = 333MHz
Status Prod
Comment
Pkg Pins WBGA(84)
Temp. Grade A2 = Automotive Grade (-40°C to +105°C)
Solder Type L = SnAgCu
Generation B = B
Number Of Words 160 = 16M
CL (CAS Latency) D = 5
Operating Voltage Range DR = 1.8V DDR2
Bus Width 16 = x16
Package Type B = BGA
Product Family 46 = DDR/DDR2/DDR3/DDR4 Automotive grade
Outpack Tape on Reel

IS46DR16160B-3DBLA2-TR Features

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
  • JEDEC standard 1.8V I/O (SSTL_18-compatible)
  • Double data rate interface: two data transfers per clock cycle
  • Differential data strobe (DQS, DQS)
  • 4-bit prefetch architecture
  • On chip DLL to align DQ and DQS transitions with CK
  • 4 internal banks for concurrent operation
  • Programmable CAS latency (CL) 3, 4, 5, 6 and 7 sup- ported
  • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5 and 6 supported
  • WRITE latency = READ latency - 1 tCK
  • Programmable burst lengths: 4 or 8
  • Adjustable data-output drive strength, full and re- duced strength options
  • On-die termination (ODT) OPTIONS
  • Configuration: 16Mx16 (4Mx16x4 banks) IS43/46DR16160B
  • Package: 84-ball TW-BGA (8mm x 12.5mm) Timing
    • Cycle time 2.5ns @CL=5 DDR2-800D 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D 3.75ns @CL=4 DDR2-533C 5.0ns @CL=3 DDR2-400B

Overview

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS46DR16160B-3DBLA2 6,147 IS46DR16160B-37CBLA1-TR
IS46DR16160B-37CBA1 IS46DR16160B-3DBLA1 6,970
IS46DR16160B-37CBA1-TR IS46DR16160B-3DBLA1-TR 1,408
IS46DR16160B-37CBLA1