IS66WVH16M8DALL-200B2LI

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Density 128M
Org 16Mx8
Vcc 1.7-1.95V
Status Prod
Pkg Pins BGA(24)
Speed Mhz 200
Comment Previous Rev IS66/67WVH16M8ALL
Package Code B2 = 24-ball TFBGA with PSC/PSC#
Density Configuration 16M8 = 128Mb /16M x8
ROHS Version L = true
Revision D = D
Product Type WVH = HyperRAM
Temperature Range I = Industrial (-40°C to 85°C)
Speed 200 = 200 MHz
Vdd(V) ALL = 1.8V
Item 66 = Pseudo SRAM/HyperRAM™

IS66WVH16M8DALL-200B2LI Features

  • Industry Standard Serial Interface
  • Low Power with Wide Temp. Ranges
  • - Single Voltage Supply IS25LE: 2.30V to 3.60V, 133MHz (max) IS25WE: 1.70V to 1.95V - 24 mA Active Read Current - 42 µA Standby Current - 5 µA Deep Power Down - Temp Grades: - Temp Grades: Extended: -40°C to +105°C Auto Grade (A3): -40°C to +125°C
  • Advanced Security Protection
  • - Software and Hardware Write Protection - Advanced Sector/Block Protection - Top/Bottom Block Protection - Power Supply Lock Protection - 4x256 Byte Dedicated Security Area with OTP User-lockable Bits - 128 bit Unique ID for Each Device (Call Factory)
  • Industry Standard Pin-out & Packages(1)
  • - M =16-pin SOIC 300mil(2) - L = 8-contact WSON 8x6mm(2) - G = 24-ball TFBGA 6x8mm (4x6 ball array)(2) - H = 24-ball TFBGA 6x8mm (5x5 ball array)(2) Notes: 1. Call Factory for other package options available. 2. For optional 512 Byte Page size with 256 KB Block size, see the Ordering Information. - IS25LE01G: 1Gbit/128Mbyte - IS25WE01G: 1GMbit/128Mbyte - 3 or 4 Byte Addressing Mode - Supports Standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI - Software & Hardware Reset - Supports Serial Flash Discoverable Parameters (SFDP)
  • High Performance Serial Flash (SPI)
  • - 50MHz Normal Read - Up to133Mhz Fast Read: 133MHz (max) for 3.0V, 104MHz (max) for 1.8V - Up to 66MHz DTR (Dual Transfer Rate) - Equivalent Throughput of 532 Mb/s - Selectable Dummy Cycles - Configurable Drive Strength - Supports SPI Modes 0 and 3 - More than 100,000 Erase/Program Cycles - More than 100-year Data Retention - 1-bit ERROR Detection and Correction per 64-bit boundary (with ECC)
  • Flexible & Efficient Memory Architecture
  • - Chip Erase with Uniform Sector/Block Erase (4/32/64KB or 4/32/256 KB)(2) - Program 1 to 256 or 512 Byte per Page(2) - Program/Erase Suspend & Resume

Overview

The IS25LE01G and IS25WE01G Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions). The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66.5Mbytes/s of data throughput. The IS25xE series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation. Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory. QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64K/256Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention. Automatic ECC Protection (1-bit Error Correction) applies per every 64-bit to maximize reliability. When ECC is ON, the device allows only single programming operation to each 8-byte ECC boundary between erase operations.

 

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