IS42S81600J-5TL

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Density	128M
Org	16Mx8
Vcc	3.3V
Type	SDR
Refresh	4K
Speed	5 = 200MHz
Status	S=NOW
Comment
Pkg Pins	TSOP2(54)
Temp. Grade	blank = Commercial Grade (0°C to +70°C)
Solder Type	L = 100% matte Sn
Number Of Words	1600 = 16M
Operating Voltage Range	S = 3.3V SDR
Generation	J = J
Bus Width	8 = x8
Package Type	T = TSOP
Product Family	42 = SDR Commercial/Industrial grade

IS42S81600J-5TL Features

Clock frequency: 200, 166, 143 MHz ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and
Fully synchronous; all signals referenced to a outputs signals refer to the rising edge of the clock input. positive clock edge The 128Mb SDRAM is organized as follows.
Internal bank for hiding row access/precharge IS42/45S81600J IS42/45S16800J
Power supply 4M x8 x4 Banks 2M x16 x4 Banks VDD & VDDQ: 3.3V
LVTTL interface KEY TIMING PARAMETERS
Programmable burst length Parameter -5 -6 -7 Unit
- (1, 2, 4, 8, full page) Clk Cycle Time
Programmable burst sequence: CAS Latency = 3 5 6 7 ns Sequential/Interleave CAS Latency = 2 10 10 7.5 ns
Auto Refresh (CBR) Clk Frequency
Self Refresh CAS Latency = 3 200 166 143 Mhz CAS Latency = 2 100 100 133 Mhz
4096 refresh cycles every 16 ms (A2 grade) or Access Time from Clock 64 ms (Commercial, Industrial, A1 grade) CAS Latency = 3 5 5.4 5.4 ns
Random column address every clock cycle CAS Latency = 2 6.5 6.5 5.4 ns
Programmable CAS latency (2, 3 clocks) ADDRESS TABLE
Burst read/write and burst read/single write operations capability Parameter 8M x 16 16M x 8 Configuration 2M x 16 x 4 banks 4M x 8 x 4 banks
Burst termination by burst stop and precharge Refresh Count Com./Ind. 4K / 64ms 4K / 64ms command A1 4K / 64ms 4K / 64ms OPTIONS A2 4K / 16ms 4K / 16ms
Green Package: Row Addresses A0
- A11 A0
- A11 54-pin TSOP II Column A0
- A8 A0
- A9 54-ball TF-BGA (8mm x 8mm) Addresses

Description	Stock Qty	Available Qty	Description	Stock Qty	Available Qty
IS42S81600J-5TL-TR			IS42S81600J-5TLI-TR
IS42S81600J-5TLI