IS42S81600J-5TL-TR
Features
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Clock frequency: 200, 166, 143 MHz ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
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Fully synchronous; all signals referenced to a outputs signals refer to the rising edge of the clock input.
positive clock edge The 128Mb SDRAM is organized as follows.
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Internal bank for hiding row access/precharge
IS42/45S81600J IS42/45S16800J
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Power supply
4M x8 x4 Banks 2M x16 x4 Banks
VDD & VDDQ: 3.3V
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LVTTL interface
KEY TIMING PARAMETERS
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Programmable burst length
Parameter -5 -6 -7 Unit
- (1, 2, 4, 8, full page)
Clk Cycle Time
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Programmable burst sequence: CAS Latency = 3 5 6 7 ns
Sequential/Interleave CAS Latency = 2 10 10 7.5 ns
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Auto Refresh (CBR) Clk Frequency
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Self Refresh CAS Latency = 3 200 166 143 Mhz
CAS Latency = 2 100 100 133 Mhz
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4096 refresh cycles every 16 ms (A2 grade) or
Access Time from Clock
64 ms (Commercial, Industrial, A1 grade) CAS Latency = 3 5 5.4 5.4 ns
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Random column address every clock cycle CAS Latency = 2 6.5 6.5 5.4 ns
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Programmable CAS latency (2, 3 clocks)
ADDRESS TABLE
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Burst read/write and burst read/single write
operations capability Parameter 8M x 16 16M x 8
Configuration 2M x 16 x 4 banks 4M x 8 x 4 banks
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Burst termination by burst stop and precharge
Refresh Count Com./Ind. 4K / 64ms 4K / 64ms
command
A1 4K / 64ms 4K / 64ms
OPTIONS A2 4K / 16ms 4K / 16ms
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Green Package: Row Addresses A0
- A11 A0
- A11
54-pin TSOP II Column A0
- A8 A0
- A9
54-ball TF-BGA (8mm x 8mm) Addresses