IS43DR32801B-3DBLI-TR

容量	256M
規格	8Mx32
電壓	1.8V
類型	DDR2
刷新	8K
速度	3 = 333MHz
狀態	Prod
評注
腳位數	BGA(126)
温度等级	I = Industrial Grade (-40°C to +85°C)
焊料類型	L = SnAgCu
字數	801 = 8M
CL（CAS延遲）	D = 5
工作電壓範圍	DR = 1.8V DDR2
Generation	B = B
總線寬度	32 = x32
腳位/封裝	B = BGA
產品系列	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
外包裝	Tape on Reel

數據表

索取報價

IS43DR32801B-3DBLI-TR 特徵

Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, and 6 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT) OPTIONS
Configuration: 8M x 32 (IS43/46DR32801B - 8K refresh)
Package: x32: 126-ball WBGA
Timing
- Cycle time 2.5ns @CL=6, DDR2-800E 3.0ns @CL=5, DDR2-667D 3.75ns @CL=4, DDR2-533C 5.0ns @CL=3, DDR2-400B

概觀

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. The 256Mb DDR2 SDRAM is provided in a wide bus x32 format, designed to offer a smaller footprint and support compact designs.

IC 編號	庫存數量	可用數量	IC 編號	可用數量
IS43DR32801B-3DBLI	55	5,000	IS43DR32801B-37CBLI-TR
IS43DR32801B-37CBL	47	220	IS43DR32801B-3DBL	5,000
IS43DR32801B-37CBL-TR			IS43DR32801B-3DBL-TR
IS43DR32801B-37CBLI	58	37

IS43DR32801B-3DBLI-TR

IS43DR32801B-3DBLI-TR 特徵

概觀

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