IS46QR8K02S2A-083TBLA2-TR
特徵
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Dual Rank: Each rank has its own CS, ODT, and CKE
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Standard Voltage : VDD = VDDQ = 1.2V, VPP=2.5V
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Signal Integrity
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High speed data transfer rates with system frequency - Internal VREFDQ Training
up to 2400 Mbps - Read Preamble Training
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Data Integrity - Gear Down Mode
- Auto Self Refresh (ASR) by DRAM built-in TS - Per DRAM Adressability
- Auto Refresh and Self Refresh Modes - Configurable DS for system compatibility
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DRAM access bandwidth - Configurable On-Die Termination
- Separated IO gating structures by Bank Groups - Data bus Inversion (DBI) for Writes
- Self Refresh Abort - ZQ Calibration for DS/ODT impedance accuracy via external
- Fine Granularity Refresh ZQ pad (240 ohm +/- 1%)
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Signal Synchronization
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Power Saving and efficiency
- Write Leveling via MR settings - POD with VDDQ termination
- Read Leveling via MPR - Command/Address Latency (CAL)
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Reliability & Error Handling - Maximum Power Saving
- Command/Address Parity - Low power Auto Self Refresh (LPASR)
- Data bus Write CRC
- MPR readout
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Operating Temperature
- Boundary Scan - Commercial (Tc = 0 oC to +95 oC)
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Speed Grade (CL-TRCD-TRP) - Industrial (Tc = -40°C to +95°C)
- 2400Mbps / 17-17-17 (-083T) - Automotive A1 (Tc = -40°C to +95°C)
- Automotive A2 (Tc = -40°C to +105°C)
- Automotive A3 (Tc = -40°C to +125°C)
PROGRAMMABLE FUNCTIONS
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Package:
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Output Driver Impedance (34/48) - 78-ball BGA (10mm x 14mm, 0.8mm ball pitch)
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CAS Write Latency (9/10/11/12/14/16/18/20)
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Additive Latency (0/CL-1/CL- 2) ADDRESS TABLE
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CS# to Command Address (3/4/5/6/8)
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Burst Type (Sequential/Interleaved) Parameter 2G x 8
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Write Recovery Time (10/12/14/16/18/20/24)
Row Addressing A0-A15
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Read Preamble (1T/2T)
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Write Preamble (1T/2T) Column Addressing A0-A9