IS67WVH8M8DBLL-100B2LA3-TR

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容量	64M
規格	8Mx8
電壓	2.7-3.6V
狀態	Prod
腳位數	BGA(24)
速度Mhz	166
評論上一篇	IS66/67WVH8M8BLL
包裝代碼	B2 = 24-ball TFBGA with PSC/PSC#
Item	67 = Automotive PSRAM/HyperRAM™
ROHS版	L = true
產品類別	WVH = HyperRAM
Revision	D = D
溫度範圍	A3 = Automotive (-40°C to +125°C)
速度	100 = 100 MHz
電壓 - 電源	BLL = 3V
密度配置	8M8 = 64Mb /8M x8
外包裝	Tape on Reel

數據表

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IS67WVH8M8DBLL-100B2LA3-TR 特徵

3.0V I/O, 11 bus signals
- Single ended clock (CK)
1.8V I/O, 12 bus signals
- Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
- Bidirectional Data Strobe / Mask
- Output at the start of all transactions to indicate refresh latency
- Output during read transactions as Read Data Strobe
- Input during write transactions as Write Data Mask
RWDS DCARS Timing
- During read transactions RWDS is offset by a second clock, phase shifted from CK
- The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye Performance Summary Read Transaction Timings Maximum Clock Rate at 1.8V VCC/VCCQ Maximum Clock Rate at 3.0V VCC/VCCQ Maximum Access Time, (tACC at 200 MHz) 200 MHz 166 MHz 40 ns High Performance Up to 400MB/s
Double-Data Rate (DDR) - two data transfers per clock
200-MHz clock rate (400 MB/s) at 1.8V VCC 166-MHz clock rate (332 MB/s) at 1.8V VCC
166-MHz clock rate (332 MB/s) at 3.0V VCC
Sequential burst transactions
Configurable Burst Characteristics ,105°C ,125°C ,105°C/125°C
- Wrapped burst lengths:
- 16 bytes (8 clocks)
- 32 bytes (16 clocks)
- 64 bytes (32 clocks)
- 128 bytes (64 clocks)
- Linear burst
- Hybrid option - one wrapped burst followed by linear burst
- Wrapped or linear burst type selected in each transaction
- Configurable output drive strength
Temperature Grade
- Industrial: -40°C to +85°C Auto (A2) Grade: -40°C to +105°C Auto (A3) Grade: -40°C to +125°C

概觀

The IS66/67WVH8M8DALL/BLL are integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 16M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and Automotive applications.

IC 編號	庫存數量	可用數量	IC 編號	庫存數量	可用數量
IS67WVH8M8DBLL-100B2LA3			IS67WVH8M8DBLL-133B1LA1-TR
IS67WVH8M8DBLL-100B1LA1			IS67WVH8M8DBLL-133B1LA2
IS67WVH8M8DBLL-100B1LA1-TR			IS67WVH8M8DBLL-133B1LA2-TR
IS67WVH8M8DBLL-100B1LA2			IS67WVH8M8DBLL-133B1LA3
IS67WVH8M8DBLL-100B1LA2-TR			IS67WVH8M8DBLL-133B1LA3-TR
IS67WVH8M8DBLL-100B1LA3			IS67WVH8M8DBLL-166B1LA1
IS67WVH8M8DBLL-100B1LA3-TR			IS67WVH8M8DBLL-166B1LA1-TR
IS67WVH8M8DBLL-100B2LA1			IS67WVH8M8DBLL-166B1LA2
IS67WVH8M8DBLL-100B2LA1-TR			IS67WVH8M8DBLL-166B1LA2-TR
IS67WVH8M8DBLL-100B2LA2			IS67WVH8M8DBLL-166B1LA3
IS67WVH8M8DBLL-100B2LA2-TR			IS67WVH8M8DBLL-166B1LA3-TR
IS67WVH8M8DBLL-133B1LA1

IS67WVH8M8DBLL-100B2LA3-TR 特徵

概觀

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