IS43LD32128C

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容量	4G
規格	128Mx32
電壓	1.2/1.8V
類型	LPDDR2
刷新	8K
狀態	S=Q2/22
腳位數	BGA(134), PoP(168)
速度Mhz	533, 400
評論上一篇
字數	128 = 128M
工作電壓範圍	LD = 1.2V - 1.8V LPDDR2
總線寬度	32 = x32
產品系列	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade

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容量

規格

128Mx32

電壓

1.2/1.8V

類型

LPDDR2

刷新

狀態

S=Q2/22

腳位數

BGA(134), PoP(168)

速度Mhz

533, 400

評論上一篇

字數

128 = 128M

工作電壓範圍

LD = 1.2V - 1.8V LPDDR2

總線寬度

32 = x32

產品系列

43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade

IS43LD32128C 特徵

Hardware Features
- SCLK Input: Serial clock input - SIO0
- SIO3: Serial Data Input or Serial Data Output - DQSM: - Output during command, address transactions as Refresh Collision Indicator - Output during read data transactions as Read Data Strobe - Input during write data transactions as Write Data Mask - RESET#: Hardware Reset pin Industrial: -40°C to +85°C
Temperature Grades
- - Extended: -40°C to +105°C - Auto (A3) Grade: -40°C to +125°C
Industry Standard PACKAGE
- B = 24-ball TFBGA 6x8mm 5x5 Array - M = 16-pin 300mil SOIC (1) - KGD (Call Factory) Note: 1. 133MHz (max.) for 16-pin SOIC package
Industry Standard Serial Interface
- Quad DDR (x4 xSPI) Interface: Command (1 byte) =SDR Address (2-byte) & Data = DDR - Low Signal Counts :7 Signal pins (CS#, SCLK, DQSM, SIO0~SIO3)
High Performance
- Double Data Rate (DDR) Operation: 200MHz (200MB/s) at 1.8V VCC (1) 133MHz (133MB/s) at 3.0V VCC - Source Synchronous Output signal during Read Operation (DQSM) - Data Mask during Write Operation (DQSM) - Configurable Latency for Read/Write Operation - Supports Variable Latency mode and Fixed Latency mode - Configurable Drive Strength - Supports Wrapped Burst mode and Continuous mode - Supports Deep Power Down mode - Hidden Refresh
Burst Operation
- Configurable Wrapped Burst Length : 16, 32, 64, and 128 - Continuous Operation: - Continues Read operation until the end of array address (No Wrapped) - Continues Write operation even after the end of array address (Wrapped to first address)

概觀

The IS66/67WVQ4M4DALL/BLL are integrated memory device containing 16Mb Pseudo Static Random Access Memory, using a self-refresh DRAM array organized as 2M words by 8 bits. The device supports Quad DDR interface, which is compatible with JEDEC standard x4 xSPI Flash. The device supports Very Low Signal Count (7 signal pins; SCLK, CS#, DQSM, and 4 SIOs), Hidden Refresh Operation, and Automotive temperature (A3, -40°C to +125°C) operation. Due to DDR operation, minimum transferred data size is a byte (8 bits) through 4 SIO pins. PERFORMANCE SUMMARY.

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IC 編號

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