IS61QDB24M18A

容量	72M
規格	4Mx18
陣	2
狀態	Prod
速度Mhz	250, 300, 333
評論上一版本	IS61QDB24M18, Application Note

容量

72M

規格

4Mx18

陣

狀態

Prod

速度Mhz

250, 300, 333

評論上一版本

IS61QDB24M18, Application Note

IS61QDB24M18A 特徵

2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability.
Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
Read address
Read enable
Write enable
Byte writes
Data-in for early writes The following are registered on the rising edge of the K# clock:
Write address
Byte writes

概觀

The synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the.

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量

IS61QDB24M18A-250B4

IS61QDB24M18A-300M3

IS61QDB24M18A-250B4-TR

IS61QDB24M18A-300M3-TR

IS61QDB24M18A-250B4I

IS61QDB24M18A-300M3I