IS61QDB24M18C-400B4I-TR

容量 72M
規格 4Mx18
2
狀態 Prod
速度Mhz 250, 300, 333, 400
評論上一版本 IS61QDB24M18A
配置 4M18 = 4M x18
ROHS版 = Leaded
突發類型 B2 = Burst 2
硅片版本 C = C
讀延時(RL) blank = 1.5 clock cycles or 2.5 clock cycles
產品類別 QD = QUAD
ODT選項 blank = No ODT
溫度範圍 I = Industrial (-40°C to +85°C)
速度 400 = 400MHz
產品系列 61 = QUAD/P DDR-2/P
包裝代碼 B4 = 165 ball BGA (13 x 15 mm)
外包裝 Tape on Reel

IS61QDB24M18C-400B4I-TR 特徵

  • 2Mx36 and 4Mx18 configuration available.
  • Separate independent read and write ports with concurrent read and write operations.
  • Max. 400 MHz clock for high bandwidth
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
  • HSTL input and output interface.
  • Full data coherency.
  • On-chip Delay-Locked loop (DLL) for wide data valid window.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array

概觀

The chronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initi- ates the read/write operation, and all internal operations are self-timed. Refer to the description of the basic operations of these.

 

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