IS49NLS96400

容量	576M
規格	64Mx9
狀態	Prod
評注
接口	Separate I/O
腳位數	BGA(144)
配置	96400 = 64M x 9
I / O類型	S = Separate I/O
產品系列	49NL = RLDRAM 2

容量

576M

規格

64Mx9

狀態

Prod

評注

接口

Separate I/O

腳位數

BGA(144)

配置

96400 = 64M x 9

I / O類型

S = Separate I/O

產品系列

49NL = RLDRAM 2

IS49NLS96400 特徵

Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and 400MHz DDR operation (800Mb/s/pin data rate) 14.4 Gb/s peak bandwidth (x18 Separate I/O at 400 MHz clock frequency) DECEMBER 2012
Reduced cycle time (15ns at 400MHz)
32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms) 8 internal banks
Non-multiplexed addresses (address multiplexing
option available) SRAM-type interface Programmable READ latency (RL), row cycle time, and burst sequence length
Balanced READ and WRITE latencies in order to optimize data bus utilization
Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
On-die termination (ODT) RTT
Operating temperature: 25-60Ω matched impedance outputs 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O IEEE 1149.1 compliant JTAG boundary scan Commercial (TC = 0° to +95°C; TA = 0°C to +70°C), Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C) OPTIONS
Package: − 144-ball FBGA (leaded) − 144-ball FBGA (lead-free) Configuration: − 64Mx9 − 32Mx18 Clock Cycle Timing:

概觀

Supply voltage Ground DQ power supply DQ Ground Supply voltage Reference voltage Termination voltage Address - A0-22 Banks - BA0-2 Input data Output data Input data clock(Differential inputs) Output data clocks(outputs) Input clocks (CK, CK#) Input data mask.

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量

IS49NLS96400-25B

6,850

IS49NLS96400-25EBL

IS49NLS96400-25B-TR

IS49NLS96400-25EBL-TR

IS49NLS96400-25BI