IS49RL18320A-093FB2L

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容量 576M
規格 32Mx18
狀態 Prod
接口 Common I/O
腳位數 BGA(168)
Cycle Time Trc 6.67, 7.5, 8
Data Rates Mbps 2400, 2133, 1866
評論上一篇 IS49RL18320
配置 18320 = 32M x 18
I / O類型 blank = RLDRAM 3
Generation A = A
產品系列 49RL = RLDRAM 3

IS49RL18320A-093FB2L 特徵

  • Configuration: - 64Mb x16 x 2 channels
  • - 8 internal banks per channel
  • Low-voltage Core and I/O Power Supplies VDD1 = 1.70-1.95V VDD2 = 1.06-1.17V VDDQ = 1.06-1.17V (LPDDR4) VDDQ = 0.57-0.65V (LPDDR4X) LVSTL(Low Voltage Swing Terminated Logic) I/O Interface Internal VREF and VREF Training
  • Dynamic ODT : DQ ODT :VSSQ Termination CA ODT :VSS Termination
  • Max. Clock Frequency : 1.6GHz (3.2Gbps)
  • 16n Pre-fetch DDR architecture
  • Single data rate (multiple cycles) command/ address bus
  • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
  • Programmable burst lengths (16 or 32)
  • ZQ Calibration
  • Operation Temperature Industrial (TC = -40°C to 95°C) Automotive, A1 (TC = -40°C to 95°C) Automotive, A2 (TC = -40°C to 105°C) Automotive, A3 (TC = -40°C to 125°C)
  • On-chip temperature sensor whose status can be read from MR4

概觀

The IS43/46LQ32640A and IS43/46LQ32640AL are 2Gbit CMOS LPDDR4 SDRAM. The device is orga- nized as 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-da- ta-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.

 

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