IS49RL36160A-083EBLI

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容量 576M
規格 16Mx36
狀態 S=NOW
評注
接口 Common I/O
腳位數 BGA(168)
Cycle Time Trc 6.67, 7.5, 8
Data Rates Mbps 2400, 2133, 1866
產品系列 49RL = RLDRAM 3
配置 36160 = 16M x 36
I / O類型 blank = RLDRAM 3
Generation A = A

IS49RL36160A-083EBLI 特徵

  • Clock cycle and tRC timing
    • 0.83ns and tRC (MIN) = 6.67ns (RL3-2400) for -083F
    • 0.83ns and tRC (MIN) = 7.5ns (RL3-2400) for -083E
    • 0.93ns and tRC (MIN) = 7.5ns (RL3-2133) for -093F
    • 0.93ns and tRC (MIN) = 8.0ns (RL3-2133) for -093E
    • 1.07ns and tRC (MIN) = 8.0ns (RL3-1866) for -107E
  • 1200 MHz DDR operation (2400 Mb/s/ball data rate)
  • Organization
    • 32 Meg x 18, and 16 Meg x 36 common I/O (CIO) 16 banks
  • 1.2V center-terminated push/pull I/O
  • 2.5V VEXT, 1.35V VDD, 1.2V VDDQ (optional 1.35V VDDQ for 2400 operation only). Reduced cycle time (tRC (MIN) = 6.67 - 8ns)
  • SDR addressing
  • Programmable READ/WRITE latency (RL/WL) and burst length
  • Data mask for WRITE commands
  • Fr DK x#) and output data clocks (QK x, QK x#)
  • On-die DLL generates CK edge-aligned data and x,
  • 64ms refresh (128K refresh per 64ms)
  • 40 Ω or 60 Ω matched impedance outputs
  • Integrated on-die termination (ODT)
  • Single or multibank writes
  • Extended operating range (200
    • 1200 MHz)
  • READ training register
  • Multiplexed and non-multiplexed addressing capa- bilities
  • Mirror function
  • Output driver and ODT calibration
  • Post Package Repar - 1 row per half bank
 

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