IS45S16400N-7TLA1

IS45S16400N-7TLA1 特徵

Clock frequency: 200, 166, 143, 133 MHz ISSI's 64Mb Synchronous DRAM is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The
Fully synchronous; all signals referenced to a synchronous DRAMs achieve high-speed data transfer positive clock edge using pipeline architecture. All inputs and outputs signals
Internal bank for hiding row access/precharge refer to the rising edge of the clock input.
Single 3.3V power supply
LVTTL interface
Programmable burst length
- (1, 2, 4, 8, full page) KEY TIMING PARAMETERS
Programmable burst sequence: Parameter -5 -6 -7 Unit Sequential/Interleave Clk Cycle Time
Self refresh modes CAS Latency = 3 5 6 7 ns CAS Latency = 2 7.5 7.5 7.5 ns
Auto refresh (CBR) Clk Frequency
4096 refresh cycles every 64 ms (Com, Ind, A1 CAS Latency = 3 200 166 143 Mhz grade) or 16ms (A2 grade) CAS Latency = 2 133 133 133 Mhz
Random column address every clock cycle Access Time from Clock
Programmable CAS latency (2, 3 clocks) CAS Latency = 3 4.8 5.4 5.4 ns
Burst read/write and burst read/single write CAS Latency = 2 5.4 5.4 5.4 ns operations capability
Burst termination by burst stop and precharge command ADDRESS TABLE OPTIONS Parameter 4M x 16
Green Package: Configuration 1M x 16 x 4 54-pin TSOP II banks 54-ball TF-BGA (8mm x 8mm) Refresh Count 60-ball TF-BGA (10.1mm x 6.4mm) Com./Ind. 4K/64ms