IS45S32200N-6TLA1-TR

IS45S32200N-6TLA1-TR 特徵

Clock frequency: 200, 166, 143, 133 MHz ISSI's 64Mb Synchronous DRAM IS42/45S32200N is organized as 524,288 bits x 32-bit x 4-bank for improved
Fully synchronous; all signals referenced to a performance.The synchronous DRAMs achieve high-speed positive clock edge data transfer using pipeline architecture. All inputs and
Internal bank for hiding row access/precharge outputs signals refer to the rising edge of the clock input.
Single 3.3V power supply
LVTTL interface KEY TIMING PARAMETERS
Programmable burst length: Parameter -5 -6 -7 Unit (1, 2, 4, 8, full page) Clk Cycle Time CAS Latency = 3 5 6 7 ns
Programmable burst sequence: Sequential/Interleave CAS Latency = 2 7.5 7.5 7.5 ns Clk Frequency
Self refresh modes CAS Latency = 3 200 166 143 Mhz
4096 refresh cycles every 16ms (A2 grade) or CAS Latency = 2 133 133 133 Mhz 64ms (Commercia, Industrial, A1 grade) Access Time from Clock
Random column address every clock cycle CAS Latency = 3 4.8 5.4 5.4 ns
Programmable CAS latency (2, 3 clocks) CAS Latency = 2 5.4 5.4 5.4 ns
Burst read/write and burst read/single write operations capability ADDRESS TABLE
Burst termination by burst stop and precharge Parameter 2M x 32 command Configuration 512K x 32 x 4 banks Refresh Count Com./Ind. 4K / 64ms OPTIONS A1 4K / 64ms
Green Packages: A2 4K / 16ms 86-pin TSOP-II Row Addresses A0
- A10 90-ball TF-BGA Column Addresses A0
- A7