SRAM is one of random access memories. SRAM has three different modes supported. Each function is described
below with Truth Table.
Device enters standby mode when deselected (CS1# HIGH or CS2 LOW). The input and output pins (I/O0-7) are
placed in a high impedance state. CMOS input in this mode will maximize saving power.
Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input
and output pins (I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW.
Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When
OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.