库存: 89
生產年份 數量
1515 89
生產年份 數量
1515 89
容量 256M
規格 16Mx16
電壓 2.5V
類型 DDR
刷新 8K
速度 5 = 200MHz
狀態 Prod
腳位數 TSOP2(66), BGA(60)
Generation F = F
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
温度等级 I = Industrial Grade (-40C to +85°C)
腳位/封裝 B = BGA
焊料類型 blank = Sn/Pb
字數 160 = 16M
工作電壓範圍 R = 2.5V DDR or 2.5V SDR
總線寬度 16 = x16
库存: 89
生產年份 數量
1515 89
生產年份 數量
1515 89

IS43R16160F-5BI 特徵

  • VDD and VDDQ: 2.5V ± 0.2V
  • SSTL_2 compatible I/O
  • Double-data rate architecture; two data transfers per clock cycle
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
  • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
  • Differential clock inputs (CK and CK)
  • DLL aligns DQ and DQS transitions with CK transitions
  • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
  • Four internal banks for concurrent operation
  • Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
  • Burst Length: 2, 4 and 8
  • Burst Type: Sequential and Interleave mode
  • Programmable CAS latency: 2, 2.5 and 3
  • Auto Refresh and Self Refresh Modes
  • Auto Precharge
  • TRAS Lockout supported (tRAP = tRCD) OPTIONS
  • Configuration(s): 8Mx32, 16Mx16, 32Mx8
  • Package(s): 144 Ball BGA (x32) 66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16)
  • Lead-free package available


ISSI’s 256-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 8-bit, 16-bit and 32-bit data word size Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. An Auto Refresh mode is provided, along with a Self Refresh mode. All I/Os are SSTL_2 compatible.



IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS43R16160F-5BI-TR IS43R16160F-6BI-TR
IS43R16160F-5BL 32 15 IS43R16160F-6BL 175 45
IS43R16160F-5BL-TR IS43R16160F-6BL-TR
IS43R16160F-5BLI 5,916 1,900 IS43R16160F-6BLI 1,140
IS43R16160F-5BLI-TR IS43R16160F-6BLI-TR
IS43R16160F-5TL 4,320 IS43R16160F-6TL 558
IS43R16160F-5TL-TR IS43R16160F-6TL-TR
IS43R16160F-5TLI IS43R16160F-6TLI 10,000
IS43R16160F-5TLI-TR 15,000 IS43R16160F-6TLI-TR