IS43R16320D-6BI

库存: 257
生產年份 數量
1404 257
可提供
生產年份 數量
1404 257
容量 512M
規格 32Mx16
電壓 2.5V
類型 DDR
刷新 8K
速度 6 = 166MHz
狀態 NR
評注
腳位數 TSOP2(66), BGA(60)
工作電壓範圍 R = 2.5V DDR or 2.5V SDR
字數 320 = 32M
腳位/封裝 B = BGA
Generation D = D
温度等级 I = Industrial Grade (-40C to +85°C)
焊料類型 blank = Sn/Pb
總線寬度 16 = x16
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
库存: 257
生產年份 數量
1404 257
可提供
生產年份 數量
1404 257

IS43R16320D-6BI 特徵

  • VDD and VDDQ: 2.5V ± 0.2V (-6)
  • VDD and VDDQ: 2.6V ± 0.1V (-5)
  • SSTL_2 compatible I/O
  • Double-data rate architecture; two data transfers per clock cycle
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
  • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
  • Differential clock inputs (CK and CK)
  • DLL aligns DQ and DQS transitions with CK transitions
  • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
  • Four internal banks for concurrent operation
  • Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
  • Burst Length: 2, 4 and 8
  • Burst Type: Sequential and Interleave mode
  • Programmable CAS latency: 2, 2.5 and 3
  • Auto Refresh and Self Refresh Modes
  • Auto Precharge
  • TRAS Lockout Supported (tRAP = tRCD ) OPTIONS
  • Configuration(s): 16Mx32, 32Mx16, and 64Mx8
  • Package(s): 144 Ball BGA (x32), 66-pin TSOP-II (x8, x16), and 60 Ball BGA (x8, x16)
  • Lead-free package

概觀

ISSI’s 512-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 8-bit, 16-bit and 32-bit data word size Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. An Auto Refresh mode is provided, along with a Self Refresh mode. All I/Os are SSTL_2 compatible. ADDRESS TABLE Parameter 16M x 32 4M x 32 x 4 Configuration banks BA0, BA1.

 

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