IS43DR16640-TR

容量	1G
規格	64Mx16
電壓	1.8V
類型	DDR2
刷新	8K
速度	800, 667, 533, 400
狀態	Contact ISSI
評注
腳位數	BGA(84)
字數	640 = 64M
工作電壓範圍	DR = 1.8V DDR2
總線寬度	16 = x16
產品系列	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
外包裝	Tape on Reel

數據表

索取報價

IS43DR16640-TR 特徵

Clock frequency up to 533MHz
8 internal banks for concurrent operation
4‐bit prefetch architecture
Programmable CAS Latency: 3, 4, 5, 6 and 7
Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6
Write Latency = Read Latency‐1
Programmable Burst Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 μs (8192 cycles/64 ms)
OCD (Off‐Chip Driver Impedance Adjustment)
ODT (On‐Die Termination)
Weak Strength Data‐Output Driver Option OPTIONS
Configuration: − 128Mx8 (16M x 8 x 8 banks) − 64Mx16 (8M x 16 x 8 banks)
Package: − 60‐ball FBGA for x8 − 84‐ball FBGA for x16 Clock Cycle Timing ‐37C PRELIMINARY INFORMATION MARCH 2010
Bidirectional differential Data Strobe (Single‐ ended data‐strobe is an optional feature)
On‐Chip DLL aligns DQ and DQs transitions with CK transitions
DQS# can be disabled for single‐ended data strobe
Read Data Strobe supported (x8 only)
Differential clock inputs CK and CK#
VDD and VDDQ = 1.8V ± 0.1V
PASR (Partial Array Self Refresh)
SSTL_18 interface
tRAS lockout supported

概觀

Input clocks Clock enable Chip Select Command control inputs Address Bank Address I/O Upper Byte Data Strobe Lower Byte Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect.

IS43DR16640-TR 特徵

概觀

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