IS46TR85120EC-125LB2LA25
特徵
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Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
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TDQS (Termination Data Strobe) supported (x8
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Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V only)
- Backward compatible to 1.5V
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OCD (Off-Chip Driver Impedance Adjustment)
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8 internal banks for concurrent operation
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Dynamic ODT (On-Die Termination)
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8n-Bit pre-fetch architecture
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Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)
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Programmable CAS Latency
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Write Leveling
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Programmable Additive Latency: 0, CL-1,CL-2
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Up to 200 MHz in DLL off mode
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Programmable CAS WRITE latency (CWL) based
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Operating temperature:
on tCK Commercial (TC = 0°C to +95°C)
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Programmable Burst Length: 4 and 8 Industrial (TC = -40°C to +95°C)
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Programmable Burst Sequence: Sequential or Automotive, A1 (TC = -40°C to +95°C)
Interleave Automotive, A2 (TC = -40°C to +105°C)
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BL switch on the fly Automotive, A25 (TC = -40°C to +115°C)
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Auto Self Refresh(ASR) Automotive, A3 (TC = -40°C to +125°C)
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Self Refresh Temperature(SRT) ECC
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Refresh Interval:
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ECC Single bit error protection (per 4-bits)
7.8 µs (8192 cycles/64 ms) Tc= -40°C to 85°C
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1-bit error correction, 2-bit error detection
3.9 µs (8192 cycles/32 ms) Tc= 85°C to 95°C
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6 ECC registers to set ECC features, to store ECC
1.95 µs (8192 cycles/16 ms) Tc= 95°C to 105°C event status
0.97 µs (8192 cycles/8 ms) Tc= 105°C to 115°C
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ECC registers can be accessed by Mode Register
0.488 µs (8192 cycles/4 ms) Tc= 115°C to 125°C
access or I2C interface by ordering option
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Partial Array Self Refresh
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ERR output signal
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Asynchronous RESET pin
OPTIONS ADDRESS TABLE
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Configuration: 512Mx8, 256Mx16 Parameter 512Mx8 256Mx16
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Green Package: Row Addressing A0-A15 A0-A14
96-ball BGA (10mm x 14mm) for x16 Column Addressing A0-A9 A0-A9
78-ball BGA (10mm x 14mm) for x8 Bank Addressing BA0-2 BA0-2
Page size 1KB 2KB