IS25LP010E-JYLA3

Buy
容量 1M
電壓 2.3-3.6V
類型 Multi I/O Quad SPI
狀態 Prod
频率 33M/104Mhz
溫度範圍 -40 to 125°C
腳位類型 SOIC, TSSOP, WSON, VVSOP, USON
替代版本文件 IS25LQ010B
工作電壓範圍 L = 2.3-3.6V
Rev Control E = E
產品系列 P = Single/Dual/Quad/QPI SPI DTR Options Available
容量 010 = 1M

IS25LP010E-JYLA3 特徵

  • Industry Standard Serial Interface
  • Low Power with Wide Temp. Ranges
  • - Single Voltage Supply: IS25LP: 2.30V to 3.60V IS25WP: 1.65V to 1.95V - 10 mA Active Read Current - 8 µA Standby Current - 1 µA Deep Power Down - Temp Grades: Extended: -40°C to +105°C Auto Grade (A3): -40°C to +125°C
  • Advanced Security Protection
  • - Software and Hardware Write Protection - Power Supply Lock Protect - 4x256-Byte Dedicated Security Area with OTP User-lockable Bits - 128 bit Unique ID for Each Device (Call Factory)
  • Industry Standard Pin-out & Packages(1)
  • - B = 8-pin SOIC 208mil (Call Factory) - N = 8-pin SOIC 150mil - D = 8-pin TSSOP (Call Factory) - V = 8-pin VVSOP 150mil (Call Factory) - K = 8-contact WSON 6x5mm (Call Factory) - Y = 8-contact USON 2x3mm - KGD (Call Factory) Note: 1. Call Factory for other package - IS25LP040E: 4Mbit/512Kbyte - IS25WP040E: 4Mbit/512Kbyte - IS25LP020E: 2Mbit/256Kbyte - IS25WP020E: 2Mbit/256Kbyte - IS25LP010E: 1Mbit/128Kbyte - IS25WP010E: 1Mbit/128Kbyte - IS25LP512E: 512Kbit/64Kbyte - IS25WP512E: 512Kbit/64Kbyte - IS25LP025E: 256Kbit/32Kbyte - IS25WP025E: 256Kbit/32Kbyte - 256 bytes per Programmable Page - Supports standard SPI, Multi-I/O SPI, and QPI - Supports Serial Flash Discoverable Parameters (SFDP)
  • High Performance Serial Flash (SPI)
  • - 50MHz Normal and 104Mhz Fast Read - 416 MHz equivalent QPI - Supports SPI Modes 0 and 3 - More than 100,000 Erase/Program Cycles - More than 20-year Data Retention
  • Flexible & Efficient Memory Architecture
  • - Chip Erase with Uniform Sector/Block Erase (4/32/64 Kbyte) - Program 1 to 256 Bytes per Page - Program/Erase Suspend & Resume - Soft RESET & In-Band RESET

概觀

The IS25LP/WP040E/020E/010E/512E/025E and Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions). The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 104MHz allow for equivalent clock rates of up to 416MHz (104MHz x 4) which equates to 52Mbytes/s of data throughput. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation. The memory array is organized into programmable pages of 256-bytes. This family supports page program mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface) supports 2- cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention. GLOSSARY Standard SPI In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions, addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the status of the device. This device supports SPI bus operation modes (0, 0) and (1, 1). Multi I/O SPI Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations. QPI The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used to switch between these two modes, regardless of the non-volatible Quad Enable (QE) bit status in the Status Register. Power Reset or Software Reset will return the device into the standard SPI mode. SI and SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during QPI mode.

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS25LP010E-JYLA3-TR IS25LP010E-JNLE
IS25LP010E-JBLE IS25LP010E-JNLE-TR
IS25LP010E-JBLE-TR IS25LP010E-JYLE
IS25LP010E-JNLA3 IS25LP010E-JYLE-TR
IS25LP010E-JNLA3-TR