IS43LD16128C-25BLI

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容量 2G
規格 128Mx16
電壓 1.2/1.8V
類型 LPDDR2
刷新 8K
狀態 S=Q3/20
腳位數 BGA(134), PoP(168)
速度Mhz 533, 400
評論上一篇
温度等级 I = Industrial Grade (-40°C to +85°C)
焊料類型 L = SnAgCu
Generation C = C
字數 128 = 128M
速度 25 = 400MHz
工作電壓範圍 LD = 1.2V - 1.8V LPDDR2
總線寬度 16 = x16
腳位/封裝 B = BGA
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade

IS43LD16128C-25BLI 特徵

  • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V
  • High Speed Un-terminated Logic(HSUL_12) I/O Interface
  • Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O)
  • Four-bit Pre-fetch DDR Architecture
  • Multiplexed, double data rate, command/ad- dress inputs
  • Eight internal banks for concurrent operation
  • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
  • Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16)
  • ZQ Calibration
  • On-chip temperature sensor to control self re- fresh rate
  • Partial
    • array self refresh(PASR)
  • Deep power-down mode(DPD)
  • Operation Temperature Commercial (TC = 0°C to 85°C) Industrial (TC = -40°C to 85°C) Automotive, A1 (TC = -40°C to 85°C) Automotive, A2 (TC = -40°C to 105°C) Automotive, A25 (TC = -40°C to 115°C)(3) OPTIONS

概觀

The IS43/46LD16128C/32640C is 2Gbit CMOS LPDDR2 DRAM. The device is organized as 8 banks of 16Meg words of 16bits or 8Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4n bits prefetched to achieve very high bandwidth.

 

相關IC编號

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IS43LD16128C-25BLI-TR IS43LD16128C-18BLI-TR
IS43LD16128C-18BL IS43LD16128C-25BL
IS43LD16128C-18BL-TR IS43LD16128C-25BL-TR
IS43LD16128C-18BLI