IS43LD16640C-18BLI

容量 1G
規格 64Mx16
電壓 1.2/1.8V
類型 LPDDR2
刷新 4K
狀態 Prod
腳位數 BGA(134), PoP(168)
速度Mhz 533, 400, 333
評論上一篇 IS43/46LD16640A
温度等级 I = Industrial Grade (-40C to +85°C)
焊料類型 L = 100% matte Sn for non-BGA or SnAgCu for BGA
Generation C = C
總線寬度 16 = 16
速度 18 = 533MHz
工作電壓範圍 LD = LPDDR2
CL(CAS延遲) B = 3
字數 64M = 64M
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade

IS43LD16640C-18BLI 特徵

  • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V
  • High Speed Un-terminated Logic(HSUL_12) I/O Interface
  • Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O)
  • Four-bit Pre-fetch DDR Architecture
  • Multiplexed, double data rate, command/ad- dress inputs
  • Eight internal banks for concurrent operation
  • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
  • Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16)
  • ZQ Calibration
  • On-chip temperature sensor to control self re- fresh rate
  • Partial
    • array self refresh(PASR)
  • Deep power-down mode(DPD)
  • Operation Temperature Commercial (TC = 0°C to 85°C) Industrial (TC = -40°C to 85°C) Automotive, A1 (TC = -40°C to 85°C) Automotive, A2 (TC = -40°C to 105°C) options

概觀

Clock: CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK. Single Data Rate (SDR) inputs, CS# and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK and CK#. The positive Clock edge is defined by the crosspoint of a rising CK and a falling CK#. The negative Clock edge is defined by the crosspoint of a falling CK and a rising CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. See Command Truth Table for command code descriptions. CKE is sampled at the positive Clock edge. Chip Select: CS# is considered part of the command code. See Command Truth Table for command code descriptions. CS# is sampled at the positive Clock edge. DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. See Command Truth Table for command code descriptions. Data Inputs/Output: Bi-directional data bus.

 

相關IC编號

IS43LD16640C-18BLI-TR IS43LD16640C-25BL-TR IS46LD16640C-18BLA1-TR IS46LD16640C-25BLA1-TR
IS43LD16640C-18BL IS43LD16640C-25BLI IS46LD16640C-18BLA2 IS46LD16640C-25BLA2
IS43LD16640C-18BL-TR IS43LD16640C-25BLI-TR IS46LD16640C-18BLA2-TR IS46LD16640C-25BLA2-TR
IS43LD16640C-25BL IS46LD16640C-18BLA1 IS46LD16640C-25BLA1