1. 矽成
  2. Mobile DRAM
  3. LPDDR2 SDRAM
  4. PowerSaver™
  5. 1.2/1.8V
  6. 1G 64Mx16
  7. BGA(134)
  8. IS43LD16640D-25BL

  IS43LD16640D-25BL

數據表
索取報價
Buy
容量 1G
規格 64Mx16
電壓 1.2/1.8V
類型 LPDDR2
刷新 4K
狀態 S=Q2/22
腳位數 BGA(134)
速度Mhz 533, 400
評論上一篇
温度等级 blank = Commercial Grade (0°C to +70°C)
焊料類型 L = SnAgCu
字數 640 = 64M
工作電壓範圍 LD = 1.2V - 1.8V LPDDR2
速度 25 = 400MHz
Generation D = D
總線寬度 16 = x16
腳位/封裝 B = BGA
產品系列 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
數據表
索取報價

IS43LD16640D-25BL 特徵

  • Hardware Features
  • - SCLK Input: Serial clock input - SIO0
    • SIO3: Serial Data Input or Serial Data Output - DQSM: - Output during command, address transactions as Refresh Collision Indicator - Output during read data transactions as Read Data Strobe - Input during write data transactions as Write Data Mask - RESET#: Hardware Reset pin
  • Temperature Grades
  • - - Auto (A2) Grade: -40°C to +105°C Industrial: -40°C to +85°C
  • Industry Standard PACKAGE
  • - B = 24-ball TFBGA 6x8mm 5x5 Array - M = 16-pin 300mil SOIC(1) - KGD (Call Factory) Note: 1. 133MHz (max.) for 16-pin SOIC package
  • Industry Standard Serial Interface
  • - Quad DDR (x4 xSPI) Interface: Command (1 byte) =SDR Address (2-byte) & Data = DDR - Low Signal Counts :7 Signal pins (CS#, SCLK, DQSM, SIO0~SIO3)
  • High Performance
  • - On chip ECC (chunk size = 4 bit): 1-bit correction and 2-bit detection - Double Data Rate (DDR) Operation: 200MHz (200MB/s) at 1.8V VCC (1) 133MHz (133MB/s) at 3.0V VCC - Source Synchronous Output signal during Read Operation (DQSM) - Data Mask during Write Operation (DQSM) - Configurable Latency for Read/Write Operation - Supports Variable Latency mode and Fixed Latency mode - Configurable Drive Strength - Supports Wrapped Burst mode and Continuous mode - Supports Deep Power Down mode - Hidden Refresh
  • Burst Operation
  • - Configurable Wrapped Burst Length : 16, 32, 64, and 128 - Continuous Operation: - Continues Read operation until the end of array address (No Wrapped) - Continues Write operation even after the end of array address (Wrapped to first address)

概觀

The IS66/67WVQ2M4EDALL/BLL are integrated memory device containing 8Mb Pseudo Static Random Access Memory, using a self-refresh DRAM array organized as 1M words by 8 bits. The device supports Quad DDR interface, which is compatible with JEDEC standard x4 xSPI Flash. The device supports Very Low Signal Count (7 signal pins; SCLK, CS#, DQSM, and 4 SIOs) + optional ERR, Hidden Refresh Operation, and Automotive temperature (A2, -40°C to +105°C) operation. Due to DDR operation, minimum transferred data size is a byte (8 bits) through 4 SIO pins. PERFORMANCE SUMMARY.

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS43LD16640D-25BL-TR IS43LD16640D-18BLI-TR
IS43LD16640D IS43LD16640D-25BLI
IS43LD16640D-18BL IS43LD16640D-25BLI-TR
IS43LD16640D-18BL-TR IS43LD16640D-TR
IS43LD16640D-18BLI