IS61DDP2B21M18A-300M3I

容量 18M
規格 1Mx18
2
狀態 Prod
速度Mhz 300, 333, 400, 450
評論上一版本 2.0 Cycle Read
配置 1M18 = 1M x18
ROHS版 = Leaded
突發類型 B2 = Burst 2
硅片版本 A = A
讀延時(RL) 2 = 2.0 clock cycles
產品類別 DDP = DDR-IIP, Common I/O
ODT選項 blank = No ODT
溫度範圍 I = Industrial (-40°C to +85°C)
速度 300 = 300MHz
產品系列 61 = QUAD/P DDR-2/P
包裝代碼 M3 = 165-ball BGA (15 x 17 mm)

IS61DDP2B21M18A-300M3I 特徵

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Read/write address
  • Read enable
  • Write enable
  • Byte writes
  • Data-in for first burst address
  • Data-Out for first burst address The following are registered on the rising edge of the K# clock:
  • Boundary scan using limited set of JTAG 1149.1
  • Byte writes functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user-supplied precision resistor.
  • Data Valid Pin (QVLD).
  • ODT (On Die Termination) feature is supported
  • optionally on data input, K/K#, and BWx#. The end of top mark (A/A1/A2) is to define options. IS61DDP2B251236A : Don’t care ODT function and pin connection IS61DDP2B251236A1 : Option1 IS61DDP2B251236A2 : Option2 Refer to more detail description at page 6 for each ODT option.
  • Data-in for second burst address

概觀

The 18Mb IS61DDP2B251236A/A1/A2 and IS61DDP2B21M18A/A1/A2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS61DDP2B21M18A-300M3I-TR IS61DDP2B21M18A1-300M3
IS61DDP2B21M18A-300B4 IS61DDP2B21M18A1-300M3-TR
IS61DDP2B21M18A-300B4-TR IS61DDP2B21M18A1-300M3I
IS61DDP2B21M18A-300B4I IS61DDP2B21M18A1-300M3I-TR
IS61DDP2B21M18A-300B4I-TR IS61DDP2B21M18A1-300M3L
IS61DDP2B21M18A-300B4L IS61DDP2B21M18A1-300M3L-TR
IS61DDP2B21M18A-300B4L-TR IS61DDP2B21M18A1-300M3LI
IS61DDP2B21M18A-300B4LI IS61DDP2B21M18A1-300M3LI-TR
IS61DDP2B21M18A-300B4LI-TR IS61DDP2B21M18A1-333B4
IS61DDP2B21M18A-300M3 IS61DDP2B21M18A2-300B4
IS61DDP2B21M18A-300M3-TR IS61DDP2B21M18A2-300B4-TR
IS61DDP2B21M18A-300M3L 10,000 IS61DDP2B21M18A2-300B4I
IS61DDP2B21M18A-300M3L-TR IS61DDP2B21M18A2-300B4I-TR
IS61DDP2B21M18A-300M3LI 10,000 IS61DDP2B21M18A2-300B4L
IS61DDP2B21M18A-300M3LI-TR IS61DDP2B21M18A2-300B4L-TR
IS61DDP2B21M18A-333B4 IS61DDP2B21M18A2-300B4LI
IS61DDP2B21M18A-333B4-TR IS61DDP2B21M18A2-300B4LI-TR
IS61DDP2B21M18A1-300B4 IS61DDP2B21M18A2-300M3
IS61DDP2B21M18A1-300B4-TR IS61DDP2B21M18A2-300M3-TR
IS61DDP2B21M18A1-300B4I IS61DDP2B21M18A2-300M3I
IS61DDP2B21M18A1-300B4I-TR IS61DDP2B21M18A2-300M3I-TR
IS61DDP2B21M18A1-300B4L IS61DDP2B21M18A2-300M3L
IS61DDP2B21M18A1-300B4L-TR IS61DDP2B21M18A2-300M3L-TR
IS61DDP2B21M18A1-300B4LI IS61DDP2B21M18A2-300M3LI
IS61DDP2B21M18A1-300B4LI-TR IS61DDP2B21M18A2-300M3LI-TR
顯示全部 (168)