IS61QDB21M36A-250M3-TR

容量 36M
規格 1Mx36
2
狀態 Prod
速度Mhz 250, 300, 333
評論上一版本 IS61QDB21M36
產品類別 QD = QUAD
突發類型 B2 = Burst 2
ODT選項 A = A
溫度範圍 blank = Commercial (0C to 70°C)
讀延時(RL) blank = 1.5 clock cycles or 2.5 clock cycles
速度 250MHz = 250MHz
包裝代碼 M3 = 165-ball BGA (15 x 17 mm)
配置 1M36 = 1M x36
外包裝 Tape on Reel

IS61QDB21M36A-250M3-TR 特徵

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Read address
  • Read enable
  • Write enable
  • Byte writes
  • Data-in for early writes The following are registered on the rising edge of the K# clock:
  • Write address
  • Byte writes

概觀

The Mb synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the.

 

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