IS61QDPB21M18A2-250M3LI-TR

容量 18M
規格 1Mx18
2
狀態 Prod
速度Mhz 250, 300, 333
評論上一版本 2.5 Cycle Read Latency
產品類別 QDP = QUADP
ROHS版 L = true
突發類型 B2 = Burst 2
ODT選項 A2 = A2
溫度範圍 I = Industrial (-40C to +85°C)
讀延時(RL) blank = 1.5 clock cycles or 2.5 clock cycles
速度 250MHz = 250MHz
包裝代碼 M3 = 165-ball BGA (15 x 17 mm)
配置 1M18 = 1M x18
外包裝 Tape on Reel

IS61QDPB21M18A2-250M3LI-TR 特徵

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.5 Cycle read latency. Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
  • Data valid pin (QVLD).
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte Write capability.
  • Fine ball grid array (FBGA) package option: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user-supplied precision resistor.
  • ODT (On Die Termination) feature is supported
  • optionally on data input, K/K#, and BWx#. The end of top mark (A/A1/A2) is to define options. IS61QDPB251236A : Don’t care ODT function and pin connection IS61QDPB251236A1 : Option1 IS61QDPB251236A2 : Option2 Refer to more detail description at page 6 for each ODT option. OCTOBER 2014 and are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the for a description of the basic operations of these SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Read and write performed in double data rate. The following are registered internally on the rising edge of the K clock:
  • Read address
  • Read enable
  • Write enable
  • Data-in for early writes The following are registered on the rising edge of the K# clock:
  • Write address
  • Byte writes

概觀

The 18MB IS61QDPB251236A/A1/A2 and IS61QDPB21M18A/A1/A2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operation of these QUADP (Burst of 2) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Read and write performed in double data rate. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered half a cycle earlier than the write address. The first data-in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the K clock. The K and K# clocks are used to time the data-outs. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interface.

 

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