容量 18M
規格 512Kx36
電壓 3.3V
VccQ 2.5/3.3V
狀態 Prod
tKQ(ns) 2.6, 3.1
腳位數 QFP(100), BGA(165)
速度Mhz 250, 200
評論上一版本 P/DCD, IS61LPD51236A

IS61LPD51236B-200B2LI 特徵

  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth control expansion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Double cycle deselect
  • Snooze MODE for reduced-power standby
  • JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages
  • Power supply: LPD: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) VPD: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) VVPD: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%) JTAG Boundary Scan for BGA packages
  • Commercial, Industrial and Automotive temperature support Lead-free available


The 18Mb product family features high-speed, low- power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPD/VPD/VVPD51236B are organized as 524,288 words by 36bits. The IS61LPD/VPD/VVPD102418B are organized as 1,048,576 words by 18bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge- triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (/BWE) input combined with one or more individual byte write signals (/BWx). In addition, Global Write (/GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either /ADSP (Address Status Processor) or /ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the /ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.



IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS61LPD51236B-200B2LI-TR IS61LPD51236B-250B2-TR
IS61LPD51236B-200B2 IS61LPD51236B-250B2I
IS61LPD51236B-200B2-TR IS61LPD51236B-250B2I-TR
IS61LPD51236B-200B2I IS61LPD51236B-250B2L
IS61LPD51236B-200B2I-TR IS61LPD51236B-250B2L-TR
IS61LPD51236B-200B2L IS61LPD51236B-250B2LI
IS61LPD51236B-200B2L-TR IS61LPD51236B-250B2LI-TR
IS61LPD51236B-200B3 IS61LPD51236B-250B3
IS61LPD51236B-200B3-TR IS61LPD51236B-250B3-TR
IS61LPD51236B-200B3I IS61LPD51236B-250B3I
IS61LPD51236B-200B3I-TR IS61LPD51236B-250B3I-TR
IS61LPD51236B-200B3L IS61LPD51236B-250B3L
IS61LPD51236B-200B3L-TR IS61LPD51236B-250B3L-TR
IS61LPD51236B-200B3LI IS61LPD51236B-250B3LI
IS61LPD51236B-200B3LI-TR IS61LPD51236B-250B3LI-TR
IS61LPD51236B-200TQ IS61LPD51236B-250TQ
IS61LPD51236B-200TQ-TR IS61LPD51236B-250TQ-TR
IS61LPD51236B-200TQI IS61LPD51236B-250TQI
IS61LPD51236B-200TQI-TR IS61LPD51236B-250TQI-TR
IS61LPD51236B-200TQL IS61LPD51236B-250TQL
IS61LPD51236B-200TQL-TR IS61LPD51236B-250TQL-TR
IS61LPD51236B-200TQLI IS61LPD51236B-250TQLI
IS61LPD51236B-200TQLI-TR IS61LPD51236B-250TQLI-TR