容量 72M
規格 2Mx32
電壓 3.3V
VccQ 2.5/3.3V
狀態 Prod
tKQ(ns) 3.1
腳位數 QFP(100)
速度Mhz 200
評論上一版本 P/SCD

IS61LPS204832B-200TQ2LI 特徵

  • Internal self-timed write cycle
  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth ex- pansion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • JTAG Boundary Scan for PBGA package
  • Power Supply LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) VVPS: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
  • JEDEC 100-Pin TQFP, 119-ball PBGA, and 165-ball PBGA packages


The 72Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and net- working applications. The IS61LPS/VPS204836B and IS64LPS204836B are organized as 2,096,952 words by 36 bits. The IS61LPS204832B is organized as 2,096,952 words by 32 bits. The IS61LPS/VPS409618B is organized as 4,193,904 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high- drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.



IS61LPS204832B-200TQ2LI-TR IS61LPS204832B-200TQ2-TR IS61LPS204832B-200TQ2L-TR IS61LPS204832B-200TQL-TR
IS61LPS204832B-200TQ IS61LPS204832B-200TQ2I IS61LPS204832B-200TQI IS61LPS204832B-200TQLI
IS61LPS204832B-200TQ-TR IS61LPS204832B-200TQ2I-TR IS61LPS204832B-200TQI-TR IS61LPS204832B-200TQLI-TR
IS61LPS204832B-200TQ2 IS61LPS204832B-200TQ2L IS61LPS204832B-200TQL